Pixel readout with partitioned analog-to-digital conversion systems and methods

Patent metadata

Field	Value
Publication number	US-11044422-B2
Application number	US-201916505260-A
Country	US
Kind code	B2
Filing date	Jul 8, 2019
Priority date	Jan 13, 2017
Publication date	Jun 22, 2021
Grant date	Jun 22, 2021

Abstract

Techniques are disclosed for systems and methods for facilitating pixel readout with partitioned analog-to-digital conversion. A device includes a detector, a capacitor coupled to the detector, a counter circuit coupled to the capacitor, a reset circuit coupled to the capacitor, and a processing circuit. The detector is configured to detect electromagnetic radiation associated with a scene and generate an associated detection signal. The capacitor is configured to, during an integration period, accumulate a voltage based on the detection signal. The counter circuit is configured to, during the integration period, adjust a counter value based on a comparison of the voltage and a reference voltage. The reset circuit is configured to, during the integration period, reset the capacitor based on the comparison. The processing circuit is configured to generate a digital detector output based on the counter value when the integration period has elapsed. Related methods are also provided.

First claim

What is claimed is:

1. A device, comprising:
a detector configured to detect electromagnetic radiation associated with an incident scene and generate a detection signal based on the detected electromagnetic radiation;
a first capacitor coupled to the detector, wherein the first capacitor is configured to, during an integration period, accumulate a first voltage based on the detection signal;
a comparator configured to, during the integration period, compare the first voltage with a reference voltage to determine whether the first voltage exceeds the reference voltage;
a first switch configured to couple the detector to a first input node of the comparator in a first switching configuration of the device;
a second switch configured to couple the detector to a second input node of the comparator when in a second switching configuration of the device;
a counter circuit coupled to the first capacitor, wherein the counter circuit is configured to, during the integration period, adjust a counter value based on a comparison of the first voltage with the reference voltage, wherein the counter circuit is coupled to the first capacitor and the first input node of the comparator;
a first reset circuit coupled to the first capacitor, wherein the first reset circuit is configured to, during the integration period, reset the first capacitor based on the comparison; and
a processing circuit configured to generate a digital detector output based at least on the counter value when the integration period has elapsed.

2. The device of claim 1 , further comprising:
a second capacitor configured to receive a residual voltage on the first capacitor when the integration period has elapsed, wherein the processing circuit is configured to generate the digital detector output based on at least on the counter value and the residual voltage.

3. The device of claim 2 , further comprising:
a sample/hold circuit configured to hold the residual voltage when the integration period has elapsed and at least partially concurrently with a second voltage being accumulated by the first capacitor, wherein the sample/hold circuit comprises the second capacitor and a switch; and
a second reset circuit coupled to the second capacitor and configured to reset the second capacitor when the residual voltage is read out to at least one of an analog bus or a buffer,
wherein:
the device comprises an infrared imaging device configured to capture an infrared image associated with the incident scene,
the digital detector output comprises a first plurality of bits indicative of the counter value and a second plurality of bits indicative of a digitized representation of the residual voltage, and
the digital detector output is associated with at least one pixel of the infrared image.

4. A device, comprising:
a detector configured to detect electromagnetic radiation associated with an incident scene and generate a detection signal based on the detected electromagnetic radiation;
a first capacitor coupled to the detector, wherein the first capacitor is configured to, during an integration period, accumulate a first voltage based on the detection signal;
a counter circuit coupled to the first capacitor, wherein the counter circuit is configured to, during the integration period, adjust a counter value based on a comparison of the first voltage with a reference voltage;
a comparator configured to, during the integration period, compare the first voltage at a first input node of the comparator with the reference voltage at a second input node of the comparator to determine whether the first voltage exceeds the reference voltage, wherein the comparator is coupled to the first capacitor and the counter circuit;
a second capacitor coupled to the comparator;
a control signal generator circuit configured to generate a plurality of control signals;
a first switch configured to selectively couple the first capacitor to the second capacitor based on a first control signal from the control signal generator circuit;
a first reset circuit coupled to the first capacitor, wherein the first reset circuit is configured to, during the integration period, reset the first capacitor based on the comparison and in response to a second control signal from the control signal generator circuit;
a second switch configured to selectively couple the second input node to the second capacitor based on a third control signal from the control signal generator circuit;
a third switch configured to selectively couple a node at the reference voltage to the first input node based on the third control signal; and
a processing circuit configured to generate a digital detector output based at least on the counter value when the integration period has elapsed.

5. The device of claim 4 , further comprising:
wherein the comparator is configured to:
receive the first voltage at the first input node of the comparator;
receive the reference voltage at the second input node of the comparator; and
provide a comparator output signal via an output node of the comparator;

the device further comprising:
a fourth switch configured to selectively couple the output node of the comparator to the second input node of the comparator based on the third control signal,

wherein:
the comparator is in a unity-gain feedback mode when the output node and the second input node are coupled via the fourth switch, and
the second capacitor is configured to capture an offset voltage associated with the comparator when the first switch is open, the second switch is closed, the third switch is closed, and the fourth switch is closed.

6. The device of claim 1 , further comprising:
a second capacitor coupled to the second input node of the comparator;
a control signal generator circuit configured to generate a control signal in response to each adjustment of the counter value to cause transitioning between the first switching configuration and the second switching configuration; and
wherein during the integration period:
when in the first switching configuration, the first capacitor is configured to accumulate the first voltage based on the detection signal; and
when in the second switching configuration, the second capacitor is configured to accumulate the first voltage based on the detection signal.

7. The device of claim 6 , further comprising:
a first transistor coupled to the first capacitor;
a second transistor coupled to the second capacitor;
a third transistor connected to the first transistor;
a fourth transistor connected to the second transistor and third transistor;
a first comparator switch configured to couple a drain of the third transistor to a gate of the third transistor when in the first switching configuration;
a second comparator switch configured to couple a drain of the fourth transistor to a gate of the fourth transistor when in the second switching configuration;
a third switch configured to couple a node at the reference voltage to the first input node when in the second switching configuration;
a fourth switch configured to couple a node at the reference voltage to the second input node when in the first switching configuration;
a fifth switch configured to couple the fourth transistor to the counter circuit when in the first switching configuration; and
a sixth switch configured to couple the third transistor to the counter circuit when in the second switching configuration,
wherein:
a gate of the first transistor is coupled to the first capacitor,
a gate of the second transistor is coupled to the second capacitor,
the drain of the third transistor is connected to a drain of the first transistor,
the drain of the fourth transistor is connected to a drain of the second transistor, and
the gate of

Assignees

• Flir Systems

Inventors

• Simolon Brian B
• Cannata Robert F
• Schlesselmann John D
• Nussmeier Mark T
• Kurth Eric A

Classifications

• G01J5/34 Primary

  using capacitors, e.g. pyroelectric capacitors · CPC title

• G01J1/46 Primary

  using a capacitor · CPC title

• H04N23/23

  from thermal infrared radiation · CPC title

• H04N25/21

  for transforming thermal infrared radiation into image signals · CPC title

• H04N25/772

  comprising A/D, V/T, V/F, I/T or I/F converters · CPC title