Systems, methods and apparatuses for device attestation based on speed of computation

Patent metadata

Field	Value
Publication number	US-11044093-B2
Application number	US-201916240371-A
Country	US
Kind code	B2
Filing date	Jan 4, 2019
Priority date	Mar 15, 2013
Publication date	Jun 22, 2021
Grant date	Jun 22, 2021

Abstract

The systems, methods and apparatuses described herein provide a computing device that is configured to attest itself to a communication partner. In one aspect, the computing device may comprise a communication port configured to receive an attestation request from the communication partner, and an application-specific integrated circuit (ASIC). The ASIC may be configured to receive the attestation request, which may include a nonce. The ASIC may be further configured to generate a verification value, capture data representing a state of computation of the ASIC when the verification value is being generated, and send the verification value and captured data to the communication port to be transmitted back to the communication partner. The verification value may be a computation result of a predefined function taking the nonce as an initial value. In another aspect, the communication partner may be configured to attest the computing device using speed of computation attestation.

First claim

What is claimed is:

1. A computer-implemented method comprising:
receiving, by a computer, an attestation request comprising one or more computation parameters including a nonce generated at a server;
generating, by the computer, a verification value, wherein the verification value is a computation result of a function taking the nonce as an initial value;
capturing, by the computer, additional data representing at least a first and a second intermediate result of the function, wherein the first intermediate result is an output of a first sequence of one or more operations comprising the function and the second intermediate result is an output of a second sequence of one or more operations comprising the function, and wherein the first sequence of operations and the second sequence of operations are different from one another; and
sending, by the computer, the verification value and the additional data to the server.

2. The method of claim 1 , wherein the computer comprises a communication port that communicates data with the server, wherein the computer receives the attestation request via the communication port, and wherein the computer sends the verification value and the additional data to the server via the communication port.

3. The method of claim 1 , wherein at least one of the first sequence of operations and the second sequence of operations comprises a symmetric encryption operation using an encryption key.

4. The method of claim 3 , further comprising receiving, by the computer, the encryption key from the server.

5. The method of claim 1 , wherein at least one sequence of operations includes at least one of a cryptographic hash operation and an encryption operation.

6. The method of claim 1 , wherein the computer comprises a dedicated computing module that performs the function, and wherein the method further comprises forwarding, by the computer, the one or more computation parameters of the attestation request to the dedicated computing module.

7. The method of claim 6 , further comprising receiving, by the computer, from the dedicated computing module the verification value and the additional data.

8. The method of claim 6 , wherein the dedicated computing module comprises at least one of an application-specific integrated circuit (ASIC) and a field programmable gate array (FPGA).

9. The method of claim 1 , wherein the server determines that the verification value is received within a predetermined time threshold, wherein the server performs the function taking the nonce as an input value, and wherein the server determines that the verification value satisfies an expected value.

10. The method of claim 1 , wherein the server determines that the verification value is received within a predetermined time threshold, and wherein the server performs the first sequence of one or more operations comprising the function taking the nonce as a first input value to determine whether the first intermediate result is equal to a first expected value and in parallel performs the second sequence of one or more operations comprising the function taking the first intermediate result as a second input value to determine whether the second intermediate result is equal to a second expected value.

11. A computing device comprising:
a communication port configured to communicate data with a server; and
one or more circuits configured to:
receive via the communication port an attestation request comprising one or more computation parameters including a nonce generated at the server;
generate a verification value, wherein the verification value is a computation result of a function taking the nonce as an initial value;
capture additional data representing at least a first and a second intermediate result of the function, wherein the first intermediate result is an output of a first sequence of one or more operations comprising the function and the second intermediate result is an output of a second sequence of one or more operations comprising the function, and wherein the first sequence of operations and the second sequence of operations are different from one another; and
send the verification value and the additional data to the server via the communication port.

12. The computing device of claim 11 , wherein at least one of the first sequence of operations and the second sequence of operations comprises a symmetric encryption operation using an encryption key.

13. The computing device of claim 12 , wherein the one or more circuits are further configured to receive the encryption key from the server via the communication port.

14. The computing device of claim 11 , wherein at least one sequence of operations includes at least one of a cryptographic hash operation and an encryption operation.

15. The computing device of claim 1 , wherein the one or more circuits of the computing device comprise a dedicated computing module that performs the function.

16. The computing device of claim 15 , wherein the one or more circuits are further configured to forward the one or more computation parameters of the attestation request to the dedicated computing module.

17. The computing device of claim 16 , wherein the one or more circuits are further configured to receive from the dedicated computing module the verification value and the additional data.

18. The computing device of claim 16 , wherein the dedicated computing module comprises at least one of an application-specific integrated circuit (ASIC) and a field programmable gate array (FPGA).

19. The computing device of claim 1 , wherein the server determines that the verification value is received within a predetermined time threshold, wherein the server performs the function taking the nonce as an input value, and wherein the server determines that the verification value satisfies an expected value.

20. The computing device of claim 19 , wherein the server determines that the verification value is received within a predetermined time threshold, and wherein the server performs the first sequence of one or more operations comprising the function taking the nonce as a first input value to determine whether the first intermediate result is equal to a first expected value and in parallel performs the second sequence of one or more operations comprising the function taking the first intermediate result as a second input value to determine whether the second intermediate result is equal to a second expected value.

Assignees

• Ologn Technologies Ag

Inventors

• Ignatchenko Sergey

Classifications

• H04L63/1466

  Active attacks involving interception, injection, modification, spoofing of data unit addresses, e.g. hijacking, packet injection or TCP sequence number attacks · CPC title

• H04L9/3234 Primary

  involving additional secure or trusted devices, e.g. TPM, smartcard, USB or software token (network architectures or network communication protocols for supporting authentication of entities using an additional device in a packet data network H04L63/0853) · CPC title

• H04W12/61

  Time-dependent · CPC title

• H04L63/126

  the source of the received data · CPC title

• H04L63/108

  when the policy decisions are valid for a limited amount of time · CPC title