Analog-to-digital converter and associated chip

Patent metadata

Field	Value
Publication number	US-11043961-B2
Application number	US-202016985115-A
Country	US
Kind code	B2
Filing date	Aug 4, 2020
Priority date	Mar 12, 2019
Publication date	Jun 22, 2021
Grant date	Jun 22, 2021

Abstract

The present application discloses an ADC (10). The ADC has an A/D conversion operation mode and a measurement operation mode. The ADC includes an input terminal (100), a DAC (104), and an output terminal (102). The input terminal is configured to receive an analog signal. The output terminal is configured to output a digital signal. The DAC includes a plurality of D/A conversion units. When the ADC operates in the A/D conversion operation mode, the ADC is configured to convert the analog signal into the digital signal, and when the ADC operates in the measurement operation mode, the digital signal related to a ratio of a capacitance of the D/A conversion unit to be measured to a total capacitance of the plurality of D/A conversion units.

First claim

What is claimed is:

1. An analog-to-digital converter (ADC), having an analog-to-digital (A/D) conversion operation mode and a measurement operation mode, wherein the ADC comprises:
an input terminal, configured to receive an analog signal;
an output terminal, configured to output a digital signal;
a digital-to-analog converter (DAC), comprises a plurality of digital-to-analog (D/A) conversion units, respectively having a unit input terminal and a unit output terminal, wherein the unit output terminals of the plurality of D/A conversion units are coupled to one another, and the plurality of D/A conversion units generates an output signal according to the unit input terminals of the plurality of D/A conversion units;
an input path selection module, coupled between the input terminal and the DAC, wherein when the ADC operates in the measurement operation mode, the input path selection module couples the unit input terminal of a D/A conversion unit to be measured among the plurality of D/A conversion units to a first reference voltage, and couples the unit input terminals of the other D/A conversion units among the plurality of D/A conversion units to a second reference voltage; and
a processing circuit, coupled between the DAC and the output terminal, wherein the processing circuit is configured to generate the digital signal according to the output signal, wherein the processing circuit includes:
a loop filter, coupled to the DAC, and generating a loop filter signal based on the output signal;
a quantizer, configured to generate a quantized signal based on the loop filter signal;
a decimation filter, configured to generate the digital signal according to the quantized signal;
an integration module, configured to generate the digital signal including a ratio according to the quantized signal; and
an output path selection module, configured to selectively couple the quantized signal to the decimation filter or the integration module;

wherein when the ADC operates in the A/D conversion operation mode, the ADC is configured to convert the analog signal into the digital signal, and when the ADC operates in the measurement operation mode, the digital signal is related to the ratio of a capacitance of the D/A conversion unit to be measured to a total capacitance of the plurality of D/A conversion units.

2. The ADC of claim 1 , wherein when the ADC operates in the measurement operation mode, each unit output terminal of the plurality of D/A conversion units is coupled to the second reference voltage, and the D/A conversion unit to be measured stores charges to be distributed based on the first reference voltage and the second reference voltage.

3. The ADC of claim 2 , wherein when the ADC operates in the measurement operation mode, the other D/A conversion units are free from storing charges.

4. The ADC of claim 1 , wherein when the ADC operates in the A/D conversion operation mode, the output path selection module couples the quantized signal to the decimation filter, and when the ADC operates in the measurement operation mode, the output path selection module couples the quantized signal to the integration module.

5. The ADC of claim 1 , wherein the loop filter comprises a low-pass filter.

6. An analog-to-digital converter (ADC), having an analog-to-digital (A/D) conversion operation mode and a measurement operation mode, wherein the ADC comprises:
an input terminal, configured to receive an analog signal;
an output terminal, configured to output a digital signal;
a digital-to-analog converter (DAC), comprises a plurality of digital-to-analog (D/A) conversion units, respectively having a unit input terminal and a unit output terminal, wherein the unit output terminals of the plurality of D/A conversion units are coupled to one another, and the plurality of D/A conversion units generates an output signal according to the unit input terminals of the plurality of D/A conversion units;
an input path selection module, coupled between the input terminal and the DAC, wherein when the ADC operates in the measurement operation mode, the input path selection module couples the unit input terminal of a D/A conversion unit to be measured among the plurality of D/A conversion units to a first reference voltage, and couples the unit input terminals of the other D/A conversion units among the plurality of D/A conversion units to a second reference voltage; and
a processing circuit, coupled between the DAC and the output terminal, wherein the processing circuit is configured to generate the digital signal according to the output signal
wherein when the ADC operates in the A/D conversion operation mode, the ADC is configured to convert the analog signal into the digital signal, and when the ADC operates in the measurement operation mode, the digital signal is related to a ratio of a capacitance of the D/A conversion unit to be measured to a total capacitance of the plurality of D/A conversion units; and
wherein the loop filter and the integration module have a reset function, and when the ADC operates in the measurement operation mode, a first D/A conversion unit of the plurality of D/A conversion units is used as the D/A conversion unit to be measured, and after obtaining the digital signal comprising the ratio by conversion, the loop filter and the integration module are reset, and then a second D/A conversion unit of the plurality of D/A conversion units is used as the D/A conversion unit to be measured.

7. The ADC of claim 6 , wherein the loop filter comprises:
an integrator, comprising a capacitor; and
a reset switch, connected in parallel with the capacitor,
wherein the loop filter is reset by conducting the reset switch.

8. The ADC of claim 1 , wherein each of the plurality of D/A conversion units comprises a capacitor, and the measurement operation mode comprises a first stage and a second stage that operate alternatingly,
wherein in the first stage, the D/A conversion unit to be measured stores the charges to be distributed by coupling the capacitor of the D/A conversion unit to be measured between the first reference voltage and the second reference voltage, and
in the second stage, re-distributing the charges to be distributed to the respective capacitor of the plurality of D/A conversion units by coupling one terminal of the respective capacitor of the plurality of D/A conversion units to the second reference voltage, and coupling the other terminal of the respective capacitor of the plurality of D/A conversion units to the first reference voltage or the third reference voltage.

9. The ADC of claim 8 , wherein the second reference voltage is a common mode voltage, and the third reference voltage is a ground voltage.

10. The ADC of claim 1 , wherein the processing circuit further comprises:
a data weighted averaging circuit, coupled between the quantizer and the DAC, and configured to selectively conduct the plurality of D/A conversion units based on the quantized signal.

11. The ADC of claim 1 , wherein the processing circuit further comprises:
an increasing data weighted averaging circuit, coupled between the quantizer and the DAC, and configured to selectively conduct the plurality of D/A conversion units based on the quantized signal.

12. A chip, comprising: an ADC, having an analog-to-digital (A/D) conversion operation mode and a measurement operation mode, wherein the ADC includes:
an input terminal, configured to receive an analog signal;
an output terminal, configured to output a digital signal;
a digital-to-analog converter (DAC), comprises a plurality of digital-to-analog (D/A) conversion units, respectively having a unit input terminal and a unit outp

Assignees

• Shenzhen Goodix Tech Co Ltd

Inventors

• Ng Si Herng
• Wang Wen-Chi

Classifications

• H03M3/464 Primary

  Details of the digital/analogue conversion in the feedback path · CPC title

• H03M3/462

  Details relating to the decimation process (decimation filters in general H03H17/0416, H03H17/0621) · CPC title

• H03M3/424

  the quantiser being a multiple bit one · CPC title

• H03M3/388

  by storing corrected or correction values in one or more digital look-up tables · CPC title

• H03M1/806

  with equally weighted capacitors which are switched by unary decoded digital signals · CPC title