Method and apparatus for calibration of voltage controlled oscillator

Patent metadata

Field	Value
Publication number	US-11043953-B2
Application number	US-202016866445-A
Country	US
Kind code	B2
Filing date	May 4, 2020
Priority date	Sep 30, 2016
Publication date	Jun 22, 2021
Grant date	Jun 22, 2021

Abstract

A method and apparatus for performing a two-point calibration of a VCO in a PLL is disclosed. The method includes determining a first steady state tuning voltage of the VCO with no modulation voltage applied. Thereafter, an iterative process may be performed wherein a modulation voltage is applied to the VCO (along with the tuning voltage) and a modified divisor is applied to the divider circuit in the feedback loop. During each iteration, after the PLL is settled, the tuning voltage is measured and a difference between the current value and the first value is determined. If the current and first values of the turning voltage are not equal, another iteration may be performed, modifying at least one of the modulation voltage and the divisor, and determining the difference between the current and first values of the tuning voltage.

First claim

What is claimed is:

1. A circuit comprising:
a phase-locked loop (PLL) having a voltage-controlled oscillator (VCO) configured to generate a periodic signal based on a tuning voltage, wherein the PLL includes a first injection point and a second injection point;
a calibration circuit configured to calibrate the PLL over one or more iterations until a difference between a steady-state value of the tuning voltage and an updated value of the tuning voltage is less than a threshold, wherein during ones of the one or more iterations, the calibration circuit is configured to:
cause a modulation voltage to be provided to the first injection point and a modified divisor to be concurrently provided to the second injection point;
determine if the difference between the steady-state value of the tuning voltage and the updated value of the tuning voltage is less than the threshold; and
perform at least one additional iteration, using new values for the modulation voltage and the modified divisor, if the difference is greater than the threshold.

2. The circuit of claim 1 , wherein the calibration circuit is further configured to, between iterations, cause a modulation voltage value of zero and an unmodified divisor to be provided to the first and second injection points, respectively.

3. The circuit of claim 1 , wherein the calibration circuit is configured to, in response to determining the difference between the steady-state value of the tuning voltage and the updated value of the tuning voltage is less than the threshold, designate final values of the modulation voltage and the modified divisor as calibrated values, wherein the calibrated values correspond to a desired shift of a frequency of the periodic signal.

4. The circuit of claim 1 , further comprising:
a first mapping circuit coupled to receive, from the calibration circuit, a digital representation of a desired shift of a frequency of the periodic signal, wherein the first mapping circuit is configured to generate a first digital value representative of a modulation voltage corresponding to the desired shift of frequency; and
a second mapping circuit coupled to receive, from the calibration circuit, the digital representation of the desired shift of frequency, wherein the second mapping circuit is configured to generate, based on the desired shift of frequency, a second digital value used to generate the modified divisor.

5. The circuit of claim 4 , wherein the calibration circuit is further configured to cause a scaling factor to be applied to the first digital value to generate a third digital value, and wherein the circuit further includes a digital-to-analog converter (DAC) configured to generate the modulation voltage using the third digital value.

6. The circuit of claim 5 , wherein the calibration circuit is configured to generate the scaling factor based on one or more measurements of the tuning voltage.

7. The circuit of claim 4 , wherein the calibration circuit includes a digital-to-analog converter configured to generate the modulation voltage using the first digital value.

8. The circuit of claim 4 , wherein the calibration circuit is configured to apply one or more scaling factors to the digital representation of the desired frequency shift, wherein the second mapping circuit is configured to generate the second digital value based on the desired frequency shift and the one or more scaling factors.

9. The circuit of claim 1 , further comprising:
a loop filter of the PLL coupled to provide the tuning voltage to the VCO; and
an analog-to-digital converter (ADC) configured to generate a digital representation of the tuning voltage, wherein the calibration.

10. The circuit of claim 9 , wherein the calibration circuit includes an accumulator circuit configured to record an average value of the tuning voltage for a given interval based on the digital representation.

11. A method comprising:
performing, over one or more iterations, a calibration of a phase-locked loop (PLL) having first and second injection points, wherein the PLL includes a voltage-controlled oscillator (VCO) configured to generate a periodic signal based on a tuning voltage, and wherein performing the calibration comprises:
providing a modulation voltage to the first injection point;
providing, concurrent with providing the modulation voltage, a modified divisor to the second injection point;
measuring a modified value of the tuning voltage;
determining a difference between the modified value of the tuning voltage and a steady-state value of the tuning voltage; and
if the difference is greater than a threshold, repeating providing the modulation voltage, providing the modified divisor, the measuring, and the determining, using new values of the modulation voltage and the modified divisor.

12. The method of claim 11 , further comprising:
providing the modulation voltage at a value of zero between iterations of the calibration; and
providing an unmodified divisor to the second injection point between iterations of the calibration.

13. The method of claim 11 , further comprising:
designating the modulation voltage and modified divisor values as calibrated values if the difference is less than or equal to the threshold; and
operating a transmitter circuit that includes the PLL, wherein operating the transmitter circuit includes performing frequency shifts of the periodic signal using the calibrated values.

14. The method of claim 11 , further comprising:
generating, using a calibration circuit, a first digital value indicative of a desired frequency shift;
generating, using the first digital value, a second digital value indicative of a modulation voltage corresponding to the desired frequency shift; and
generating, using the first digital value, a third digital value indicative of the modified divisor corresponding to the desired frequency shift.

15. The method of claim 11 , further comprising:
converting, using an analog-to-digital converter (ADC), the modified value of the tuning voltage into a digital value; and
determining, in a calibration circuit using the digital value, the difference between the modified value of the tuning voltage and the steady-state value of the tuning voltage.

16. A system comprising:
a digital signal processor configured to generate digital signals to cause variation of an amplitude and a frequency of a signal to be transmitted;
a phase-locked loop (PLL) having voltage-controlled oscillator (VCO) and a divider, wherein, during operation, a transmitter is configured to cause a desired frequency shift by causing the PLL to vary a frequency of a periodic signal produced by the PLL, wherein the VCO is configured to generate a periodic signal based on a tuning voltage; and
a calibration circuit configured to calibrate the PLL, over one or more iterations, to determine a modulation voltage value and modified divisor value to produce the desired frequency shift, herein during ones of the one or more iterations, the calibration circuit is configured to:
cause a modulation voltage to be provided to the VCO and a modified divisor to be concurrently provided to the divider;
determine if a difference between a steady-state value of the tuning voltage and a modified value of the tuning voltage is less than or equal to a threshold; and
repeat performing iterations, using new values for the modulation voltage and the modified divisor, for ones of the one or more iterations in which the difference is greater than the threshold; and
discontinue performing iterations if, for a given iteration, the difference between is less th

Assignees

• Apple Inc

Inventors

• Hammerschmidt Joachim S
• Lorenz Robert G

Classifications

• H03C3/0958 Primary

  applying frequency modulation by varying the characteristics of the voltage controlled oscillator · CPC title

• H03B2201/025

  the means being an electronic switch for switching in or out oscillator elements · CPC title

• H03L7/0996

  Selecting a signal among the plurality of phase-shifted signals produced by the ring oscillator · CPC title

• H03L7/0805

  the loop being adapted to provide an additional control signal for use outside the loop · CPC title

• H03C3/0991

  including calibration means or calibration methods · CPC title