Method and system for providing a configurable logic device having a programmable DSP block

Patent metadata

Field	Value
Publication number	US-11043950-B2
Application number	US-201916586891-A
Country	US
Kind code	B2
Filing date	Sep 27, 2019
Priority date	Sep 27, 2019
Publication date	Jun 22, 2021
Grant date	Jun 22, 2021

Abstract

A programmable logic device (“PLD”) contains programmable digital signal processing (“DSP”) blocks operable to be selectively programmed to perform one or more logic functions. The PLD, in one embodiment, includes configurable logic blocks (“LBs”), an input and output (“I/O”) block, and programmable DSP blocks. The configurable LBs are able to be selectively programmed to perform one or more logic functions. The I/O block includes I/O ports for facilitating data transfer. The programmable DSP blocks are configured to perform various predefined logic functions. Each of the programmable DSP blocks, in one aspect, includes at least one configurable DSP which, in one embodiment, includes a 27×18 multiplier and a 12×12 multiplier.

First claim

What is claimed is:

1. A semiconductor device able to be selectively programmed to perform one or more logic functions utilizing a programmable digital signal processing (“DSP”) block, the device comprising:
a plurality of configurable logic blocks (“LBs”) able to be selectively programmed to perform one or more logic functions; and
at least one programmable DSP block coupled to the plurality of configurable LBs and configured to have at least one configurable DSP (“CDSP”) which allows a user to program size of operands, wherein the CDSP contains a first multiplier and a second multiplier, the first multiplier operable to multiple a first set of operands with a first set of bit numbers, the second multiplier operable to multiple a second set of operands with a second set of bit numbers.

2. The device of claim 1 , wherein the first set of bit numbers are different than the second set of bit numbers.

3. The device of claim 1 , wherein the first set of operands includes a 27-bit operand and an 18-bit operand (27×18).

4. The device of claim 3 , wherein the second set of operands is 12 bits by 12 bits (12×12) operands.

5. The device of claim 1 , wherein the first multiplier is a 27×18 multiplier and the second multiplier is a 12×12 multiplier.

6. The device of claim 1 , wherein the first multiplier includes a pre-adder (“Padd”) to perform an addition before multiplication.

7. The device of claim 1 , wherein the CDSP includes one or more hybrid multiplier blocks (“HMBs”) wherein each of the HMBs includes a shifter configured to shift at least a portion of data to a neighboring CDSP.

8. The device of claim 1 , wherein the CDSP includes a data output (“DOUT”) component configured to combine a first product result from the first multiplier and a second product result from the second multiplier before outputting an output.

9. The device of claim 1 , further comprising an input and output (“I/O”) block coupled to the plurality of configurable LBs and configured to have a plurality of I/O ports for facilitating data transfer.

10. A programmable semiconductor integrated circuit fabricated on a single microchip able to provide various digital signal processing functions comprising the device of claim 1 .

11. A method of programmable digital signal processing (“DSP”) block in a field programmable gate array (“FPGA”) configured to processing data, comprising:
configuring a programmable DSP to determine size of operands in accordance with signals provided by a user;
receiving a first A operand having a first A bit number and a first B operand having a first B bit number;
receiving a second A operand having a second A bit number and a second B operand having a second B bit number;
multiplying, by a first multiplier in a programmable DSP block, the first A operand by the first B operand to produce a first product result;
multiplying, by a second multiplier in the programmable DSP block, the second A operand by the second B operand to produce a second product result; and
combining the first product result and the second product result to generate an output result for the programmable DSP block.

12. The method of claim 11 , further comprising:
receiving a C operand having a C bit number; and
adding the C operand with the first A operand to generate a pre-add summation.

13. The method of claim 11 , wherein receiving a first A operand includes receiving an operand represented in 27 bits.

14. The method of claim 13 , wherein receiving a first B operand includes receiving an operand represented in 18 bits.

15. The method of claim 14 , wherein receiving a second A operand includes receiving an operand represented in 12 bits and receiving a second B operand includes receiving an operand represented in 12 bits.

16. The method of claim 11 , further comprising shifting at least a portion of the first A operand to a neighboring DSP block.

17. The method of claim 11 , further receiving control signals from external block for configuring the programmable DSP block.

18. A programmable logic device having a programmable digital signal processing (“DSP”) block operable to be selectively programmed to perform one or more logic functions, the device comprising:
a plurality of configurable logic blocks (“LBs”) able to be selectively programmed to perform one or more logic functions;
an input and output (“I/O”) block coupled to the plurality of configurable LBs and configured to have a plurality of I/O ports for facilitating data transfer; and
a plurality of configurable DSPs (“CDSPs”) coupled to the plurality of configurable LBs and configured to perform one or more selected predefined logic functions, wherein each of the plurality of CDSPs allows a user to program size of operands and includes a 27×18 multiplier and a 12×12 multiplier.

19. The device of claim 18 , wherein the 27×18 multiplier includes a pre-adder (“Padd”) configured to perform an addition before multiplication.

20. The device of claim 18 , wherein each of the plurality of CDSPs includes a shifter configured to shift at least a portion of data to a neighboring CDSP.

21. The device of claim 18 , wherein each of the plurality of the CDSPs includes a data output (“DOUT”) component configured to combine a first product result from the 27×18 multiplier and a second product result from the 12×12 multiplier.

Assignees

• Liu Jianhua
• Chen Chienkuang
• Gowin Semiconductor Corp

Inventors

• Liu Jianhua
• Chen Chienkuang

Classifications

• H03K19/17728 Primary

  Reconfigurable logic blocks, e.g. lookup tables · CPC title

• H03K19/17712

  one of the matrices at least being reprogrammable · CPC title

• H03K19/17744

  for input/output signals · CPC title