Bandwidth enhanced amplifier for high frequency CML to CMOS conversion

Patent metadata

Field	Value
Publication number	US-11043948-B1
Application number	US-202016802684-A
Country	US
Kind code	B1
Filing date	Feb 27, 2020
Priority date	Feb 27, 2020
Publication date	Jun 22, 2021
Grant date	Jun 22, 2021

Abstract

A bandwidth enhanced amplifier for high frequency CML To CMOS conversion is disclosed. In some implementations, an improved CML to CMOS converter includes a differential amplifier having a first and a second input transistors, and a first and a second load transistors. The first input transistor is coupled in series with the first load transistor, and the second input transistor is coupled in series with the second load transistor. The improved CML to CMOS converter further includes a first capacitor and a second capacitor. The first capacitor is coupled directly between a gate of the first input transistor and a gate of the first load transistor.

First claim

What is claimed is:

1. A current mode logic (CML) to complementary metal oxide semiconductor (CMOS) converter, comprising:
a differential amplifier having
a first and a second input transistors,
a first and a second load transistors, wherein the first input transistor is coupled in series with the first load transistor, and the second input transistor is coupled in series with the second load transistor,
a first transistor coupled in parallel with the first load transistor, and
a resistor having a first and a second terminals; and

a first capacitor coupled directly between a gate of the first input transistor and a gate of the first load transistor, the first terminal of the resistor coupled to a gate of the first transistor and the second terminal of the resistor coupled to the gate of the first load transistor and the first capacitor.

2. The CML to CMOS converter of claim 1 , further comprising:
a second capacitor coupled between a gate of the second input transistor and a gate of the second load transistor.

3. The CML to CMOS converter of claim 1 , wherein the first capacitor is configured to provide a feed forward path through the first load transistor.

4. The CML to CMOS converter of claim 1 , wherein the first capacitor has a capacitance of about 50 fF.

5. The CML to CMOS converter of claim 1 , wherein the differential amplifier further comprises:
a second transistor coupled in series with the first transistor such that a drain of the second transistor is coupled to a drain of the first transistor.

6. The CML to CMOS converter of claim 1 , further comprising:
a third capacitor coupled between a gate of the second transistor and a gate of the first transistor, wherein the gate of the first transistor is further coupled to a drain of the first load transistor and a drain of the first input transistor.

7. The CML to CMOS converter of claim 1 , wherein the first and the second input transistors are n-type metal oxide semiconductor (nMOS) transistors, and the first and the second load transistors are p-type metal oxide semiconductor (pMOS) transistors.

8. The CML to CMOS converter of claim 7 , wherein the differential amplifier further comprises a bias transistor coupled between sources of the first and the second input transistors and ground, and the bias transistor is an nMOS transistor.

9. The CML to CMOS converter of claim 1 , wherein the first and the second input transistors are configured to receive a pair of differential signals at their gates from a CML circuit.

10. The CML to CMOS converter of claim 9 , wherein the CML circuit includes a phase interpolator.

11. A system on chip (SoC), comprising:
a phase interpolator to adjust a phase of an input clock; and
a current mode logic (CML) to complementary metal oxide semiconductor (CMOS) converter coupled to the phase interpolator to receive output signals from the phase interpolator,
a differential amplifier having
a first and a second input transistors,
a first and a second load transistors, wherein the first input transistor is coupled in series with the first load transistor, and the second input transistor is coupled in series with the second load transistor,
a first transistor coupled in parallel with the first load transistor, and
a resistor having a first and a second terminals; and

a first capacitor coupled directly between a gate of the first input transistor and a gate of the first load transistor, the first terminal of the resistor coupled to a gate of the first transistor and the second terminal of the resistor coupled to the gate of the first load transistor and the first capacitor.

12. The SoC of claim 11 , wherein the CML to CMOS converter further comprises:
a second capacitor coupled between a gate of the second input transistor and a gate of the second load transistor.

13. The SoC of claim 11 , wherein the first capacitor is configured to provide a feed forward path through the first load transistor.

14. The SoC of claim 11 , wherein the first capacitor has a capacitance of about 50 fF.

15. The SoC of claim 11 , wherein the differential amplifier further comprises:
a second transistor coupled in series with the first transistor such that a drain of the second transistor is coupled to a drain of the first transistor.

16. The SoC of claim 11 , wherein the CML to CMOS converter further comprises:
a third capacitor coupled between a gate of the second transistor and a gate of the first transistor, wherein the gate of the first transistor is further coupled to a drain of the first load transistor and a drain of the first input transistor.

17. The SoC of claim 11 , further comprising a delay locked loop (DLL) coupled to the CML to CMOS converter to receive a clock signal from the CML to CMOS converter.

18. The SoC of claim 12 , further comprising a Serializer-Deserializer (SerDes) input/output (I/O) interface, wherein the phase interpolator and the CML to CMOS converter are part of the SerDes I/O interface.

19. A method to convert signals from a current mode logic (CML) circuit to signals usable by complementary metal oxide semiconductor (CMOS) based circuit, the method comprising:
providing a first and a second input transistors to receive a pair of differential signals from the CML circuit at gates of the first and the second input transistors, and
coupling a first load transistor in series with the first input transistor;
coupling a second load transistor in series with the second input transistor;
coupling a first transistor in parallel with the first load transistor; and
providing a first feed forward path from the first input transistor through the first load transistor, and a second feed forward path from the second input transistor through the second load transistor at high frequency, wherein providing the first feed forward path comprises
coupling a first capacitor directly between the gate of the first input transistor and a gate of the first load transistor, and
coupling a resistor between the gate of the first load transistor and a gate of the first transistor.

20. The method of claim 19 , wherein providing the second feed forward path comprises coupling a second capacitor directly between the gate of the second input transistor and a gate of the second load transistor.

Assignees

• Qualcomm Inc

Inventors

• Lekkala Suresh Naidu
• Mohamad Sajin

Classifications

• H03G1/0029

  using field-effect transistors [FET] · CPC title

• H03F2200/36

  the amplifier comprising means for increasing the bandwidth · CPC title

• H03F2203/30042

  the SEPP bias voltage being controlled by a control signal from a feedforward circuit · CPC title

• H03F2203/30111

  A resistor being added in the push stage of the SEPP amplifier · CPC title

• H03F2203/45651

  the LC comprising two cascode current sources · CPC title