Method for separately biasing power amplifier for additional power control

Patent metadata

Field	Value
Publication number	US-11043753-B2
Application number	US-201816132877-A
Country	US
Kind code	B2
Filing date	Sep 17, 2018
Priority date	Sep 18, 2017
Publication date	Jun 22, 2021
Grant date	Jun 22, 2021

Abstract

An apparatus includes a phased array antenna panel and one or more beam former circuits mounted on the phased array antenna panel. The phased array antenna panel generally comprises a plurality of antenna elements. The plurality of antenna elements are generally arranged in one or more groups. Each beam former circuit may be coupled to a respective group of the antenna elements. Each beam former circuit generally comprises a plurality of transceiver channels. Each transceiver channel generally comprises a power amplifier circuit configured, when operating in a transmit mode, to drive a respective one of the antenna elements. The power amplifier circuit generally comprises separate bias and voltage supply inputs providing additional power control.

First claim

The invention claimed is:

1. An apparatus comprising:
a phased array antenna panel comprising a plurality of antenna elements, wherein said plurality of antenna elements are arranged in one or more groups; and
one or more beam former circuits mounted on the phased array antenna panel, each beam former circuit coupled to a respective group of said antenna elements, each beam former circuit comprising (i) a combiner-splitter network coupled to a common radio frequency port and (ii) a plurality of transceiver channel circuits, each transceiver channel circuit coupled between said combiner-splitter network and a respective radio frequency input/output, each transceiver channel circuit comprising a power amplifier circuit configured, when operating in a transmit mode, to drive a respective one of said antenna elements connected to the respective radio frequency input/output, wherein said power amplifier circuit comprises separate bias and voltage supply inputs providing additional power control and said bias input to said power amplifier circuit is provided by a programmable reference current weighting structure.

2. The apparatus according to claim 1 , wherein the phased array antenna panel is configured to operate in a frequency range comprising at least one of a radio frequency band, a milli-meter wave frequency band, and a microwave frequency band.

3. The apparatus according to claim 1 , wherein the power amplifier circuit further comprises a separate bias scheme from other amplifiers of each transceiver channel circuit.

4. The apparatus according to claim 3 , wherein said separate bias scheme maintains efficiency while lowering output power of said power amplifier circuit.

5. The apparatus according to claim 1 , wherein each of the transceiver channel circuits comprises one or more amplifier circuits and at least one of said amplifier circuits has a gain controlled in response to a respective gain control signal and a bias level controlled in response to a respective bias control signal.

6. The apparatus according to claim 5 , wherein a gain value and a bias value for said at least one of said amplifier circuits is stored in respective registers associated with said at least one of said amplifier circuits.

7. The apparatus according to claim 1 , wherein said programmable reference current weighting structure is programmed by storing a bias value in a respective register associated with said power amplifier circuit.

8. The apparatus according to claim 7 , wherein said programmable reference current weighting structure comprises a number of transistors with different sizes configured to provide a number of binary steps in response to the bias value stored in said respective register associated with said power amplifier circuit.

9. The apparatus according to claim 8 , wherein said number of transistors with different sizes comprise one or more of a bipolar junction transistor (BJT), a heterojunction bipolar transistor (HBT), a metal-oxide-semiconductor field-effect-transistor (MOSFET), a pseudomorphic high electron mobility transistor (pHEMT), and/or a silicon-on-insulator (SOI) transistor.

10. A beam former architecture comprising:
a combiner-splitter network coupled to a common radio frequency port; and
a plurality of transceiver channel circuits, each transceiver channel circuit coupled between said combiner-splitter network and a respective radio frequency input/output, each transceiver channel circuit comprising a power amplifier circuit configured, when operating in a transmit mode, to drive an antenna element connected to the respective radio frequency input/output, wherein said power amplifier circuit comprises separate bias and voltage supply inputs providing additional power control and said bias input to said power amplifier circuit is provided by a programmable reference current weighting structure.

11. The beam former architecture according to claim 10 , further comprising a memory configured to store a plurality of phase, gain and bias values for each of said transceiver channel circuits.

12. The beam former architecture according to claim 10 , wherein the power amplifier circuit further comprises a separate bias scheme from other amplifiers of each transceiver channel circuit.

13. The beam former architecture according to claim 12 , wherein said separate bias scheme maintains efficiency while lowering output power of said power amplifier circuit.

14. The beam former architecture according to claim 10 , wherein said programmable reference current weighting structure is programmed by storing a bias value in a respective register associated with said power amplifier circuit.

15. The beam former architecture according to claim 14 , wherein said programmable reference current weighting structure comprises a number of transistors with different sizes configured to provide a number of binary steps in response to the bias value stored in said respective register associated with said power amplifier circuit.

16. The beam former architecture according to claim 15 , wherein said number of transistors with different sizes comprise one or more of a bipolar junction transistor (BJT), a heterojunction bipolar transistor (HBT), a metal-oxide-semiconductor field-effect-transistor (MOSFET), a pseudomorphic high electron mobility transistor (pHEMT), and/or a silicon-on-insulator (SOI) transistor.

17. A method of biasing a beam former power amplifier for additional power control comprising:
arranging a plurality of antenna elements of a phased array antenna panel in one or more groups; and
mounting one or more beam former circuits on the phased array antenna panel;
coupling each beam former circuit to a respective group of said antenna elements, wherein each beam former circuit comprises (i) a combiner-splitter network coupled to a common radio frequency port and (ii) a plurality of transceiver channel circuits, each transceiver channel circuit coupled between said combiner-splitter network and a respective radio frequency input/output, each transceiver channel circuit including a transmit channel and a receive channel comprising a power amplifier circuit configured, when operating in a transmit mode, to drive a respective one of said antenna elements connected to the respective radio frequency input/output;
distributing a first power supply voltage to said power amplifier circuit of each of the plurality of transceiver channel circuits and a second power supply voltage to circuitry of each of the plurality of transceiver channel circuits other than said power amplifier circuit; and
receiving separate bias and voltage supply inputs at said power amplifier circuit, wherein said separate bias and voltage supply inputs are configured to provide additional power control and said bias input to said power amplifier circuit is provided by a programmable reference current weighting structure.

18. The method according to claim 17 , wherein efficiency and power of said power amplifier circuit is optimized by a combination of controlling the separate bias and voltage supply inputs, either simultaneously or separately.

Assignees

• Integrated Device Tech

Inventors

• Zihir Samet
• Kanar Tumay

Classifications

• H03F3/195 Primary

  in integrated circuits · CPC title

• H03F2200/27

  A biasing circuit node being switched in an amplifier circuit · CPC title

• H03F2203/45302

  the common gate stage of a cascode dif amp being controlled · CPC title

• H03F3/245

  with semiconductor devices only · CPC title

• H01Q21/22 Primary

  Antenna units of the array energised non-uniformly in amplitude or phase, e.g. tapered array or binomial array · CPC title