Semiconductor devices and methods for fabricating the same

Patent metadata

Field	Value
Publication number	US-11043563-B2
Application number	US-201815918578-A
Country	US
Kind code	B2
Filing date	Mar 12, 2018
Priority date	Mar 12, 2018
Publication date	Jun 22, 2021
Grant date	Jun 22, 2021

Abstract

A semiconductor device includes a compound semiconductor layer disposed on a substrate, a protection layer disposed on the compound semiconductor layer, and a source electrode, a drain electrode and a gate electrode penetrating the protection layer and on the compound semiconductor layer, wherein the gate electrode is disposed between the source electrode and the drain electrode. The semiconductor device also includes a plurality of field plates disposed over the protection layer and between the gate electrode and the drain electrode, wherein the plurality of field plates are separated from each other. A method for fabricating the semiconductor device is also provided.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a compound semiconductor layer disposed on a substrate;
a first protection layer disposed on the compound semiconductor layer;
a second protection layer disposed on the first protection layer;
a source electrode, a drain electrode and a gate electrode penetrating the second protection layer and the first protection layer and on the compound semiconductor layer, wherein the gate electrode is disposed between the source electrode and the drain electrode;
a doped compound semiconductor region disposed between the gate electrode and the compound semiconductor layer, wherein the doped compound semiconductor region is embedded in the first protection layer;
a first field plate disposed between the gate electrode and the drain electrode, wherein the first field plate penetrates the second protection layer and is on the first protection layer; and
a second field plate disposed between the drain electrode and the first field plate and on the second protection layer, wherein the gate electrode, the first field plate and the second field plate are separated from each other, wherein a bottom surface of the first field plate lands on a top surface of the first protection layer, and a bottom surface of the second field plate lands on a top surface of the second protection layer, wherein the gate electrode includes an upper portion covering the top surface of the second protection layer, wherein topmost portions of the gate electrode, the first field plate, and the second field plate are coplanar with each other.

2. The semiconductor device as claimed in claim 1 , wherein the gate electrode, the first field plate and the second field plate are formed of a same metal material layer.

3. The semiconductor device as claimed in claim 1 , wherein a material of the second protection layer is different from a material of the first protection layer.

4. The semiconductor device as claimed in claim 1 , further comprising an interconnection structure disposed over the second protection layer, wherein the first field plate and the second field plate are in electrical connection with the source electrode through the interconnection structure.

5. A method for fabricating the semiconductor device as set forth in claim 1 , comprising:
forming the compound semiconductor layer on the substrate;
forming the first protection layer on the compound semiconductor layer;
forming the gate electrode penetrating the first protection layer and on the compound semiconductor layer;
forming the doped compound semiconductor region disposed between the gate electrode and the compound semiconductor layer, wherein the doped compound semiconductor region is embedded in the first protection layer;
forming a plurality of field plates over the first protection layer, wherein the plurality of field plates are separated from each other; and
forming the source electrode and the drain electrode penetrating the first protection layer and on the compound semiconductor layer, wherein the gate electrode is between the source electrode and the drain electrode, and
the plurality of field plates are between the gate electrode and the drain electrode, wherein topmost portions of the gate electrode and the plurality of field plates are coplanar with each other.

6. The method as claimed in claim 5 , wherein the gate electrode is separated from the plurality of the field plates.

7. The method as claimed in claim 5 , wherein the forming the gate electrode and the plurality of field plates comprises:
forming a first opening penetrating the first protection layer and exposing the compound semiconductor layer;
forming a metal material layer over the first protection layer and filling the first opening; and
etching the metal material layer to form the gate electrode and the plurality of field plates.

8. The method as claimed in claim 5 , wherein the plurality of field plates comprise the first field plate and the second field plate, wherein the second field plate is between the first field plate and the drain electrode.

9. The method as claimed in claim 8 , further comprising forming the second protection layer on the first protection layer, wherein the gate electrode, the source electrode and the drain electrode penetrate the second protection layer, the first field plate penetrates the second protection layer and is on the first protection layer, and the second field plate is formed on the second protection layer.

10. The method as claimed in claim 9 , wherein a material of the second protection layer is different from a material of the first protection layer.

11. The method as claimed in claim 5 , further comprising forming an interconnection structure over the first protection layer, wherein the plurality of field plates are in electrical connection with the source electrode through the interconnection structure.

Assignees

• Vanguard Int Semiconduct Corp

Inventors

• Lin Hsin-Chih
• Hung Chang-Xiang
• Huang Chia-Ching
• Lin Yung-Hao
• Lee Chia-Hao

Classifications

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D64/118

  Electrodes comprising insulating layers having particular dielectric or electrostatic properties, e.g. having static charges · CPC title

• H10D64/01

  Manufacture or treatment · CPC title

• H10D62/824

  comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions · CPC title

• H10D30/4755

  having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs · CPC title