Method of manufacturing a semiconductor device

US11043434B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11043434-B2
Application numberUS-202016743959-A
CountryUS
Kind codeB2
Filing dateJan 15, 2020
Priority dateFeb 17, 2017
Publication dateJun 22, 2021
Grant dateJun 22, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

In a manufacturing step in which a structure of target of screening is formed on a semiconductor substrate in the middle of manufacturing process before a semiconductor device is finished, screening of potential defects of a gate insulating film is performed for each wafer at one time so that the semiconductor device is caused to appear as an initial defective product when the finished semiconductor device is subjected to an electrical characteristic test. Provided are a semiconductor device, and a method of manufacturing a semiconductor device which enables reliable screening of potential defects in a short period of time.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of manufacturing a semiconductor device, the semiconductor device having a gate insulating film and a gate electrode film on a semiconductor substrate of a wafer, the method comprising: forming a first gate insulating film on the semiconductor substrate of the wafer; forming a first gate electrode film on an entire surface of the semiconductor substrate of the wafer, the semiconductor substrate of the wafer including the first gate insulating film; screening, after the forming a first gate electrode film, the first gate insulating film by generating a potential difference between the first gate electrode film which is formed on the entire surface of the semiconductor substrate of the wafer, and a back surface of the semiconductor substrate of the wafer to apply an electric field to the first gate insulating film; determining the semiconductor substrate of the wafer which has been subjected to the screening; patterning the first gate electrode film after the determining the semiconductor substrate; removing, after the patterning the first gate electrode film, the first gate insulating film which is formed on the entire surface of the semiconductor substrate of the wafer from at least a region in which a second gate insulating film is to be formed; forming, after removing the first gate insulating film, the second gate insulating film on the semiconductor substrate of the wafer; forming a second gate electrode film on the entire surface of the semiconductor substrate of the wafer, the semiconductor substrate of the wafer including the second gate insulating film; screening, after the forming a second gate electrode film, the second gate insulating film by generating a potential difference between the second gate electrode film which is formed on the entire surface of the semiconductor substrate of the wafer, and the back surface of the semiconductor substrate of the wafer to apply an electric field to the second gate insulating film; determining the semiconductor substrate of the wafer which has been subjected to the screening; and patterning the second gate electrode film after the determining the semiconductor substrate. 2. The method of manufacturing a semiconductor device according to claim 1 , further comprising repeating a plurality of times: removing, after the patterning the second gate electrode film, a gate insulating film that is previously formed; forming a new gate insulating film on the semiconductor substrate of the wafer; forming a new gate electrode film on the entire surface of the semiconductor substrate of the wafer which includes the new gate insulating film; screening, after the forming a new gate electrode film, the new gate insulating film by generating a potential difference between the new gate electrode film which is formed on the entire surface of the semiconductor substrate of the wafer, and the back surface of the semiconductor substrate of the wafer to apply an electric field to the new gate insulating film; determining the semiconductor substrate of the wafer which has been subjected to the screening; and patterning the new gate electrode film after the determining the semiconductor substrate. 3. The method of manufacturing a semiconductor device according to claim 1 , further comprising forming the gate insulating film a plurality of times so that the second gate insulating film has a thickness smaller than a thickness of the first gate insulating film or a gate insulating film that is formed later has a smaller thickness. 4. The method of manufacturing a semiconductor device according to claim 1 , further comprising applying a screening voltage for the gate insulating film that is formed a plurality of times so that a screening voltage for the second gate insulating film is higher than a screening voltage for the first gate insulating film or a screening voltage for a gate insulating film that is formed later is higher.

Assignees

Inventors

Classifications

  • in a gaseous ambient using an oxygen or a water vapour, e.g. oxidation through a layer (H10D64/01344 takes precedence) · CPC title

  • in a nitrogen-containing ambient, e.g. N2O oxidation · CPC title

  • Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

  • the insulator being formed after the semiconductor body, the semiconductor being silicon · CPC title

  • H10P74/23Primary

    characterised by multiple measurements, corrections, marking or sorting processes · CPC title

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What does patent US11043434B2 cover?
In a manufacturing step in which a structure of target of screening is formed on a semiconductor substrate in the middle of manufacturing process before a semiconductor device is finished, screening of potential defects of a gate insulating film is performed for each wafer at one time so that the semiconductor device is caused to appear as an initial defective product when the finished semicond…
Who is the assignee on this patent?
Ablic Inc
What technology area does this patent fall under?
Primary CPC classification H10P74/23. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jun 22 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).