Stripe mapping in memory

Patent metadata

Field	Value
Publication number	US-11042441-B2
Application number	US-201916458578-A
Country	US
Kind code	B2
Filing date	Jul 1, 2019
Priority date	Jun 10, 2015
Publication date	Jun 22, 2021
Grant date	Jun 22, 2021

Abstract

Examples of the present disclosure provide apparatuses and methods related to redundant array of independent disks (RAID) stripe mapping in memory. An example method comprises writing data in a number of stripes across a storage volume of a plurality of memory devices according to a stripe map; wherein each of the number of stripes includes a number of elements; and wherein the stripe map includes a number of stripe indexes to identify the number of stripes and a number of element identifiers to identify elements included in each of the number of stripes.

First claim

What is claimed is:

1. A method for stripe mapping, comprising:
performing a read error recovery operation using a first stripe map to identify a plurality of stripes that include a number of bad elements, wherein each of the plurality of stripes include each of the number of bad elements and wherein the read error recovery operation corrects data from the number of bad elements in each of the plurality of stripes using parity data, moves the corrected data to a different number of elements, and updates the first stripe map to include element identifiers of the different number of elements in each stripe of the plurality of stripes, wherein the different number of elements that store the corrected data are included in each stripe of the plurality of stripes in response to the read error recovery operation.

2. The method of claim 1 , further including performing the read error recovery operation by locating the number of bad elements in the plurality of stripes using the first stripe map and updating element identifiers for each of the plurality of stripes associated with the number of bad elements in a second stripe map.

3. The method of claim 2 , wherein further including creating the second stripe map by identifying each of the different number of elements with a page identifier.

4. The method of claim 2 , wherein the method includes updating the second stripe map by removing element identifiers of the number of bad elements from the second stripe map.

5. The method of claim 2 , wherein the method includes updating the second stripe map by replacing element identifiers of the number of bad elements with element identifiers of the different number of elements.

6. The method claim 2 , wherein the second stripe map includes a page element identifier in each of the plurality of stripes.

7. The method of claim 1 , wherein the method includes performing the read error recovery operation in response to an error correction code (ECC) operation failure.

8. An apparatus, comprising:
a number of memory devices; and
a controller coupled to the number of memory devices and configured to:
write data to the number of memory devices, wherein the data is written to elements of a plurality of stripes as defined by a first stripe map; and
perform a read error recovery operation using a second stripe map, wherein the read error recovery operation corrects data from a bad element in each of the plurality of stripes using parity data and moves the corrected data to a different element, wherein the bad element is in each of the plurality of stripes; and
update the second stripe map to include an element identifier of the different element in each stripe of the plurality of stripes, wherein the different element stores the corrected data and is included in each stripe of the plurality of stripes in response to the read error recovery operation.

9. The apparatus of claim 8 , wherein element identifiers for each element of the plurality of stripes includes channel, device, block, and page information.

10. The apparatus of claim 8 , wherein elements of each stripe of the plurality of stripes include varied bit error rates.

11. The apparatus of claim 8 , wherein elements of each stripe of the plurality of stripes are selected based on physical locations in the number of memory devices.

12. The apparatus of claim 8 , wherein the controller is configured to perform the read error recovery operation using the second stipe map to identify a portion of the plurality of stripes that each include a number of bad elements.

13. The apparatus of claim 8 , wherein the controller is configured to update the first stripe map based on the read error recovery operation.

14. A method for stripe mapping, comprising:
performing a redundant array of independent disks (RAID) read error recovery operation using a first stripe map to identify a plurality of stripes that include a bad element, wherein the bad element in each stripe of the plurality of stripes and wherein the RAID read error recovery operation corrects data in the bad element using parity data, moves the corrected data to a different element, and updates element identifiers in each stripe of the plurality of stripes to include an identifier for the different element, wherein the different element that stores the corrected data is included in each stripe of the plurality of stripes in response to the read error recovery operation.

15. The method of claim 14 , wherein the method includes creating a second stripe map by associating each of a number of stripe indexes with a portion of the elements included in each of the plurality of stripes.

16. The method of claim 14 , wherein the method includes creating a second stripe map by associating each of the plurality of stripes with a page element identifier.

17. The method of claim 14 , wherein the method includes creating a second stripe map by selecting the elements to include in the plurality of stripes based on a bit error rate associated with the elements.

18. The method of claim 14 , wherein the method includes creating a second stripe map by selecting the pages to include in the plurality of stripes based on a location of the pages within a memory device.

19. The method of claim 14 , further including writing data in the plurality of stripes includes splitting the data into a number of elements and writing the number of elements to a plurality of memory devices.

20. The method of claim 19 , further including writing the number of elements to the plurality of memory devices includes writing at least one element to each of the plurality of memory devices.

Assignees

• Micron Technology Inc

Inventors

• Mcglaughlin Edward
• Jeddeloh Joseph M

Classifications

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F11/108 Primary

  Parity data distribution in semiconductor storages, e.g. in SSD · CPC title

• G06F3/0629

  Configuration or reconfiguration of storage systems · CPC title

• G06F3/0656

  Data buffering arrangements · CPC title

• G06F11/1012 Primary

  using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence) · CPC title