Time-to-digital converter

Patent metadata

Field	Value
Publication number	US-11042126-B2
Application number	US-202016900452-A
Country	US
Kind code	B2
Filing date	Jun 12, 2020
Priority date	Dec 14, 2017
Publication date	Jun 22, 2021
Grant date	Jun 22, 2021

Abstract

A time-to-digital converter (TDC) is disclosed, which comprises a ring oscillator module and a digital error correction module. The ring oscillator module is configured to receive a sampling signal, an addressing signal, and a preset signal, and includes: a ring oscillator arranged with a plurality of inverters; a phase sampler configured to sample phase signals generated by the inverters for generating a first output signal; a counter clock generator configured to generate first and second clock signals; first and second counters configured to respectively generate first and second counter output signals; and a data sampler configured to sample the first and second counter output signals to respectively generate second and third output signals. The digital error correction module is arranged to process the first, second and third output signals for generating a digital signal.

First claim

What is claimed is:

1. A time-to-digital converter (TDC) comprising:
a ring oscillator module configured to receive a sampling signal, an addressing signal, and a preset signal, wherein the ring oscillator module includes:
(i) a ring oscillator arranged with a plurality of inverters;
(ii) a phase sampler configured to sample phase signals generated by the plurality of inverters of the ring oscillator for generating a first output signal, on receipt of the sampling signal;
(iii) a counter clock generator configured to generate a first clock signal and a second clock signal, based on receipt of the sampling signal and phase signals generated by a first inverter and a last inverter of the ring oscillator, respectively;
(iv) a first counter and a second counter configured to generate a first counter output signal and a second counter output signal, respectively, based on receipt of the first clock signal and the second clock signal, respectively; and
(v) a data sampler configured to sample the first counter output signal and the second counter output signal to generate a second output signal and a third output signal, respectively; and

a digital error correction module arranged to process the first output signal, the second output signal, and the third output signal for generating a digital signal representative of a time difference between receipt of a start signal and receipt of a stop signal by the TDC,
wherein the ring oscillator is arranged to be operated between a first mode and a second mode on receipt of the preset signal, wherein the ring oscillator is electrically switched on for a period corresponding to the time difference in the first mode, and in the second mode, the ring oscillator is electrically switched off by presetting an inverter identified based on the addressing signal.

2. The TDC of claim 1 , wherein the data sampler includes a D flip-flops circuit.

3. The TDC of claim 1 , wherein the phase sampler includes a sense-amplifier-based D flip-flops circuit.

4. The TDC of claim 1 , wherein the first output signal includes a resultant phase signal based upon the phase signals generated by the plurality of inverters.

5. The TDC of claim 1 , further comprising a digital control module arranged to receive the start signal and the stop signal for generating the sampling signal, the addressing signal, and the preset signal, wherin the digital control module includes:
a pseudo-random code generator configured to generate the addressing signal to randomly address one of the inverters of the ring oscillator as the inverter identified to be preset; and
a control signal generator configured to generate the sampling signal and the preset signal.

6. The TDC of claim 1 , wherein the addressing signal is predetermined to preset a same inverter at each conversion cycle.

7. The TDC of claim 1 , wherein the digital error correction module is configured to perform the following step for processing the first output signal, the second output signa, and the third output signal:
determining a value of the phase signal generated by the first inverter,
wherein, if the phase signal generated by the first inverter has a value of 0, the third output signal is selected for processing by the digital error correction module, or, if the phase signal generated by the first inverter has a value of 1, the second output signal is selected for processing by the digital error correction module, and wherein the second output signal is further processed using both a value of the phase signal generated by the last inverter and a predefined value associated with a corresponding inverter selected to be preset at each conversion cycle of the ring oscillator.

8. The TDC of claim 1 , wherein the counter clock generator is configured to stop the phase signals generated by the first and last inverters that are provided to the counter clock generator, and wherein stoppage of the phase signals is performed based on the sampling signal.

9. A method of time-to-digital conversion, the method comprising:
(i) generating phase signals by a plurality of inverters of a ring oscillator that includes a plurality of inverters; (ii) responsive to a sampling signal, sampling the phase signals to generate a first output signal; (iii) generating, by a counter clock generator, a first clock signal and a second clock signal, based on receipt of the sampling signal and phase signals generated by a first inverter and a last inverter of the ring oscillator, respectively; (iv) generating a first counter output signal and a second counter output signal, based on receipt of the first clock signal and the second clock signal, respectively; (v) sampling the first counter output signal and the second counter output signal to generate a second output signal and a third output signal, respectively; and (vi) processing the first output signal, the second output signal, and the third output signal to generate a digital signal representative of a time difference between receipt of a start signal and receipt of a stop signal,
wherein the method further includes operating the ring oscillator between a first mode and a second mode based on the preset signal, wherein the ring oscillator is electrically switched on for a period corresponding to the time difference in the first mode, and the ring oscillator is electrically switched off by presetting an inverter identified based on the addressing signal in the second mode.

10. The method of claim 9 , wherein step (vi) includes:
determining a value of the phase signal generated by the first inverter,
wherein, if the phase signal generated by the first inverter has a value of 0, the third output signal is selected for processing by the digital error correction module, or, if the phase signal generated by the first inverter has a value of 1, the second output signal is selected for processing by the digital error correction module, and wherein the second output signal is further processed using both a value of the phase signal generated by the last inverter and a predefined value associated with a corresponding inverter selected to be preset at each conversion cycle of the ring oscillator.

11. A time-to-digital converter (TDC) comprising:
a ring oscillator module configured to receive a sampling signal, an addressing signal, and a preset signal, the ring oscillator module includes:
(i) a ring oscillator arranged with a plurality of inverters;
(ii) a phase sampler configured to sample phase signals generated by the plurality of inverters of the ring oscillator for generating a first output signal, on receipt of the sampling signal;
(iii) a counter clock generator configured to generate a first clock signal and a second clock signal, based on receipt of the sampling signal and phase signals generated by a first inverter and a last inverter of the ring oscillator, respectively;
(iv) a first counter and a second counter configured to generate a first counter output signal and a second counter output signal, respectively, based on receipt of the first clock signal and the second clock signal, respectively; and
(v) a data sampler configured to sample the first counter output signal and the second counter output signal to generate a second output signal and a third output signal;

a digital error correction module arranged to process the first output signal, the second output signal, and the third output signal for generating a digital signal representative of a time difference between receipt of a start signal and receipt of a stop signal by the TDC,
wherein the ring oscillator is arranged to be operated between a first mode and a second mode based on the preset signal, and wherein the ring oscillator is elect

Assignees

• Huawei Int Pte Ltd

Inventors

• Yuan Chao
• Yu Rui
• Chen Xuesong
• Liu Supeng
• Yeo Theng Tee

Classifications

• G04F10/005 Primary

  Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60) · CPC title

• H03K3/0315

  Ring oscillators · CPC title

• H03L7/085

  concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) · CPC title