Bus node address verification

Patent metadata

Field	Value
Publication number	US-11038712-B2
Application number	US-202016784419-A
Country	US
Kind code	B2
Filing date	Feb 7, 2020
Priority date	Feb 27, 2019
Publication date	Jun 15, 2021
Grant date	Jun 15, 2021

Abstract

Disclosed is a method for detecting an erroneous bus node address allocation in data bus systems with auto addressing using an addressing current, such as LIN data bus systems with auto addressing. The method comprises performing auto addressing of the n bus nodes, causing an addressing current to be supplied by a bus node, sensing the data bus current by the bus nodes and determining a bus node-specific bus current measurement value, deciding, whether an addressing current flows through the respective bus node, and determining a bus node-specific addressing current presence value, transmitting the bus node-specific bus current measurement value and/or the bus node-specific addressing current presence value from the bus node to the bus master, forming a supply bus node-specific result vector from the received bus node-specific addressing current presence values, and comparing the supply bus node-specific result vector and a supply bus node-specific expectation vector.

First claim

The invention claimed is:

1. A method for verifying a correctness of previously allocated addresses to bus nodes of a serial data bus system comprising a data bus, a bus master and a plurality of bus nodes each having a respective address, wherein the data bus extends from the bus master and the bus nodes are connected to the data bus, and wherein at least some of the bus nodes comprise a respective current measuring circuit serially connected to the data bus and a respective current source for supplying a respective current into the data bus which current flows to the bus master,
the method comprising:
providing, for and/or in the bus master, allocation information regarding the allocation of the respective addresses of the bus nodes to their respective positions in the data bus and expectation information regarding the bus node or the bus nodes comprising the respective current measuring circuit, which is or are expected to detect the respective current if a respective one of these bus nodes supplies the current into the data bus via its respective current source, which current flows towards the bus master,
initiated by the bus master, causing the respective current to be supplied by one of the bus nodes comprising the respective current measuring circuit and the respective current source,
detecting by all the bus nodes comprising the respective current measuring circuit and the respective current source, whether the bus nodes respectively sense the current or not,
transmitting the detection results to the bus master by the bus nodes comprising the respective measuring circuits and the respective current sources, and
comparing, the detection results and a respective expectations information.

2. The method of claim 1 , wherein the comparison of the detection results and the respective expectation information is performed by the bus master.

3. The method of claim 1 , wherein the data bus is a linear data bus.

4. The method of claim 1 , further comprising:
causing the supply of the current by the bus node into the data bus,
detecting whether each of the bus nodes sense the current or not, the detection being performed by all of the bus nodes comprising the respective current measuring circuit and the respective current source, and
transmitting the detection results by the bus nodes to the bus master for each bus node comprising the respective current measuring circuit and the respective current source, and
comparing, the detection results and the respective expectation information in order to assess whether the bus nodes are correctly addressed.

5. The method of claim 4 wherein the comparison of the detection results and the respective expectation information is performed by the bus master.

6. The method of claim 4 , further comprising:
acknowledging the correctness of the address allocation, if the detection results correspond to the respective expectation information, and
signaling an error, if at least one of the detection results does not correspond to the respective expectation information.

7. The method of claim 6 , wherein signaling an error comprises an indication of a concrete error based on a deviation of the at least one detection result from the respective expectation information.

8. The method of claim 1 , wherein providing the allocation information comprises:
performing an address allocation process, under control of the bus master, for an automatic allocation of addresses to bus nodes to be addressed provided with the respective current measuring circuit and the respective current source, which allocation is performed sequentially in a defined order starting from a bus node to be addressed connected to the data bus at a position farthest from the bus master to a bus node to be addressed connected to the data bus at a position closest to the bus master.

9. The method of claim 8 , wherein, via its current source, each bus node to be addressed supplies current into the data bus upstream of the respective bus node with respect to the bus master via its current source or upstream of its current measuring circuit with respect to the bus master or in that, via their respective current sources, some of the bus nodes to be addressed supply current into the data bus upstream of the respective bus node with respect to the bus master or upstream of the respective current measuring circuit with respect to the bus master, whereas, via their respective current sources, the rest of the bus nodes to be addressed supply current into the data bus downstream of the current measuring circuit with respect to the bus master.

10. The method of claim 1 , wherein at least one bus node provided with the respective current measuring circuit and the respective current source is also connected to the data bus, to which bus node an address has been allocated by a manufacturer.

11. The method of claim 1 , wherein at least one bus node without a current measuring means and without a current source is also connected to the data bus, to which bus node an address has been allocated by a manufacturer.

12. A bus node of the serial data bus system provided with an address allocated by the bus master of the serial data bus system, for implementation in the method of claim 1 , comprising:
a control unit for accepting the address allocated to the bus node,
the respective current measuring circuit allocated to the bus node, for measuring a current in the data bus, and
the respective current source,
wherein, upon reception of an instruction from the bus master directed to the bus node, the control unit controls the current source to supply the current into the data bus and transmits information to the bus master as to whether the current measuring circuit allocated to the bus node detects a current flow in the data bus or not.

13. A method for operating the bus node of claim 12 , comprising:
allocating an address to the bus node,
causing, by the bus master for the verification of the correctness of the bus node address, the bus node to supply the current into the data bus,
verifying, by the bus node, whether the respective current measuring circuit allocated to the bus node and connected to the data bus measures the current flow or not, and
reporting a result of the verification to the bus master by the bus node.

Assignees

• Elmos Semiconductor Se
• Elmos Semiconductor Ag

Inventors

• Schlautmann Guido
• Schmidt André
• Heppekausen Stefanie
• Naumann Jürgen

Classifications

• H04L61/5038 Primary

  for local use, e.g. in LAN or USB networks, or in a controller area network [CAN] · CPC title

• H04L12/40019

  Details regarding a bus master · CPC title

• G06F11/221 Primary

  to test buses, lines or interfaces, e.g. stuck-at or open line faults · CPC title

• H04L12/40032 Primary

  Details regarding a bus interface enhancer · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title