Charge pump transient response optimization by controlled flying capacitor discharge during bypass to switching mode transition

Patent metadata

Field	Value
Publication number	US-11038420-B2
Application number	US-201916528906-A
Country	US
Kind code	B2
Filing date	Aug 1, 2019
Priority date	Aug 1, 2019
Publication date	Jun 15, 2021
Grant date	Jun 15, 2021

Abstract

Circuits and methods to enable wireless power transmission and reception are presented. A two-stage power converter has a boost regulator to boost an input voltage to an intermediate voltage. Moreover, the two-stage power converter may also comprise a charge pump coupled to the boost regulator to generate an output voltage based on the intermediated voltage. More particularly, the charge pump may comprise a plurality of transistor devices and a flying capacitor and the charge pump may be bypassed during a bypass mode of operation. Finally, the two-stage power converter may have control circuitry coupled to the charge pump. In particular, the control circuitry may generate a control voltage of a first transistor device of the plurality of transistor devices in order to regulate a discharge rate of the flying capacitor, during a transition phase from the bypass mode of operation to a normal mode of operation.

First claim

What is claimed is:

1. A two-stage power converter, comprising:
a boost regulator configured to boost an input voltage to an intermediate voltage;
a charge pump coupled to the boost regulator, wherein the charge pump comprises a plurality of transistor devices and a flying capacitor, wherein the charge pump is configured to generate an output voltage based on the intermediate voltage, and wherein the charge pump can be bypassed during a bypass mode of operation; and
a control circuitry coupled to the charge pump,
wherein the control circuitry is configured to generate a control voltage of a first transistor device of the plurality of transistor devices in order to regulate a discharge rate of the flying capacitor, during a transition phase from the bypass mode of operation to a normal mode of operation; and
wherein the control voltage of the first transistor device is controlled such that the first transistor device operates in a saturation mode and behaves like a voltage controlled current source during the transition phase.

2. The two-stage power converter according to claim 1 , wherein the control voltage is generated based on a voltage across the flying capacitor and a variable reference voltage.

3. The two-stage power converter according to claim 1 , wherein the control circuitry comprises:
a voltage sensing circuit configured to sense a voltage across the flying capacitor and to generate an amplified voltage that is proportional to the sensed voltage.

4. The two-stage power converter according to claim 3 , wherein the control circuitry further comprises:
an amplifier circuit configured to generate an error voltage based on a difference between the amplified voltage and a variable reference voltage.

5. The two-stage power converter according to claim 4 , wherein the variable reference voltage is controlled in accordance with a desired discharging rate of the flying capacitor.

6. The two-stage power converter according to claim 1 ,
wherein, during the normal mode of operation, the output voltage is generated to be a multiple of the intermediate voltage generated by the boost regulator; and
wherein, during the bypass mode of operation, the output voltage is equal to the intermediate voltage generated by the boost regulator.

7. The two-stage power converter according to claim 6 ,
wherein the output voltage equals twice the intermediate voltage during the normal mode of operation; and
wherein the voltage across the flying capacitor is discharged to a value that is half the output voltage during the transition phase.

8. The two-stage power converter according to claim 1 , wherein the boost regulator is configured to receive the output voltage as feedback and to adjust the intermediate voltage based on the output voltage and a desired voltage level for the output voltage.

9. The two-stage power converter according to claim 1 , wherein a time constant of a control loop of the boost regulator is shorter than a time constant of the discharge rate of the flying capacitor.

10. A two-stage power converter, comprising:
a boost regulator configured to boost an input voltage to an intermediate voltage;
a charge pump coupled to the boost regulator, wherein the charge pump comprises a plurality of transistor devices and a flying capacitor, wherein the charge pump is configured to generate an output voltage based on the intermediate voltage, and wherein the charge pump can be bypassed during a bypass mode of operation; and
a control circuitry coupled to the charge pump,
wherein the control circuitry is configured to generate a control voltage of a first transistor device of the plurality of transistor devices in order to regulate a discharge rate of the flying capacitor, during a transition phase from the bypass mode of operation to a normal mode of operation; and
wherein the control circuitry comprises:
a voltage sensing circuit configured to sense a voltage across the flying capacitor and to generate are amplified voltage that is proportional to the sensed voltage;
an amplifier circuit configured to generate an error voltage based on a difference between the amplified voltage and a variable reference voltage; and
a buffer circuit configured to generate a first intermediate supply voltage, wherein the first intermediate supply voltage is generated to be equal to or to be a scaled value of the error voltage.

11. The two-stage power converter according to claim 10 , wherein the control circuitry further comprises:
a gate driver circuit configured to generate the control voltage of the first transistor device, wherein the gate driver circuit is supplied by the first intermediate supply voltage.

12. The two-stage power converter according to claim 11 , wherein the control circuitry further comprises:
a first capacitive element; and
a refresh switching device for selectively coupling the first capacitive element to the buffer circuit,
wherein, during a first switching phase of the charge pump, the refresh switching device is in an ON state and the first capacitive element is charged by the first intermediate supply voltage; and
wherein, during a second switching phase of the charge pump, the refresh switching device is in an OFF state and the first capacitive element is coupled between a gate terminal and a source terminal of the first transistor device.

13. The two-stage power converter according to claim 10 , wherein the buffer circuit comprises:
a low-dropout (LDO) regulator including an amplifier and a pass device.

14. A two-stage power converter, comprising:
a boost regulator configured to boost an input voltage to an intermediate voltage;
a charge pump coupled to the boost regulator, wherein the charge pump comprises a plurality of transistor devices and a flying capacitor, wherein the charge pump is configured to generate an output voltage based on the intermediate voltage, and wherein the charge pump can be bypassed during a bypass mode of operation; and
a control circuitry coupled to the charge pump,
wherein the control circuity is configured to generate a control voltage of a first transistor device of the plurality of transistor devices in order to regulate a discharge rate of the flying capacitor, during a transition phase from the bypass mode of operation to a normal mode of operation; and
wherein the control circuitry comprises:
a voltage sensing circuit configured to sense a voltage across the flying capacitor and to generate an amplified voltage that is proportional to the sensed voltage;
an amplifier circuit configured to generate an error voltage based on a difference between the amplified voltage and a variable reference voltage; and
an active clamp circuit supplied by the output voltage, wherein the active clamp circuit is configured to generate a second intermediate supply voltage based on the error voltage.

15. The two-stage power converter according to claim 14 , wherein the control circuitry further comprises:
a gate driver circuit configured to generate the control voltage of the first transistor device, wherein the gate driver circuit is supplied by the second intermediate supply voltage.

16. The two-stage power converter according to claim 14 , wherein the active clamp circuit comprises:
an active clamp switching device, wherein the active clamp switching device is configured to selectively couple the flying capacitor in parallel with a second capacitive element.

17. The two-stage power converter according to claim 16 , wherein the active clamp further comprises:
a first comparator configured to generate a first sig

Assignees

• Dialog Semiconductor Uk Ltd

Inventors

• Mercer Mark
• Kanner Jeffrey

Classifications

• H02M3/073

  Charge pumps of the Schenkel-type · CPC title

• H02M1/0067

  Converter structures employing plural converter units, other than for parallel operation of the units on a single load · CPC title

• H02M3/158 Primary

  including plural semiconductor devices as final control devices for a single load · CPC title

• H02M3/07 Primary

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

• H02M1/36

  Means for starting or stopping converters · CPC title