Through gate fin isolation

Patent metadata

Field	Value
Publication number	US-11037923-B2
Application number	US-201213538935-A
Country	US
Kind code	B2
Filing date	Jun 29, 2012
Priority date	Jun 29, 2012
Publication date	Jun 15, 2021
Grant date	Jun 15, 2021

Abstract

Through gate fin isolation for non-planar transistors in a microelectronic device, such as an integrated circuit (IC). In embodiments, ends of adjacent semiconductor fins are electrically isolated from each other with an isolation region that is self-aligned to gate electrodes of the semiconductor fins enabling higher transistor packing density and other benefits. In an embodiment, a single mask is employed to form a plurality of sacrificial placeholder stripes of a fixed pitch, a first subset of placeholder stripes is removed and isolation cuts made into the semiconductor fins in openings resulting from the first subset removal while a second subset of the placeholder stripes is replaced with gate electrodes.

First claim

What is claimed is:

1. A microelectronic device, comprising:
a first gate electrode disposed over a first semiconductor fin wherein the first semiconductor fin has a length greater than a width, wherein the length is the distance between ends of the fin;
a second gate electrode disposed over a second semiconductor fin wherein the second semiconductor fin has a length greater than a width, wherein the length is the distance between ends of the fin, wherein the first and second semiconductor fins consist essentially of silicon,
a first isolation region disposed between the first and second gate electrodes and separating adjacent ends of the first and second semiconductor fins, and wherein the first isolation region directly contacts the adjacent ends of the first and second semiconductor fins, wherein the first semiconductor fin and the second semiconductor fin are bifurcated portions of a single semiconductor feature,
a first embedded epitaxial semiconductor region in a portion of the first semiconductor fin between the first gate electrode and the first isolation region,
a second embedded epitaxial semiconductor region in a portion of the second semiconductor fin between the second gate electrode and the second isolation region, the first and second embedded epitaxial semiconductor regions consisting essentially of silicon germanium, and
wherein the first gate electrode, second gate electrode, and first isolation region are substantially parallel with longitudinal centerlines at a substantially equal pitch,
wherein the first semiconductor fin and the second semiconductor fin have longitudinal centerlines that are substantially coincident, and wherein a surface of the first gate electrode facing away from the first fin is substantially coplanar with a surface of the first isolation region, and wherein the first isolation region has a transverse width that is no larger than a width of a gate stack that includes both the first gate electrode and a gate dielectric layer in contact with the first gate electrode, wherein the width of the gate stack is parallel along a same direction as the transverse width of the first isolation region.

2. The microelectronic device of claim 1 , further comprising a second isolation region disposed on an end of the first semiconductor fin opposite the first isolation region, wherein centerlines of the first and second isolation regions define an isolation region pitch that is an integer multiple of a minimum pitch for the gate electrodes.

3. The microelectronic device of claim 2 , wherein centerlines of the first and second gate electrodes define a gate electrode pitch that is an integer multiple of the minimum gate electrode pitch.

4. The microelectronic device of claim 3 , wherein the gate electrode pitch is substantially equal to the isolation region pitch with the gate electrodes and isolation regions forming stripes at a minimum stripe pitch.

5. The microelectronic device of claim 1 , further comprising a third and fourth semiconductor fins, wherein the first gate electrode is disposed over both the first and third semiconductor fins and the second gate electrode is disposed over both the second and fourth semiconductor fins, and wherein the first isolation region separates adjacent ends of the first and second semiconductor fins and the third and fourth semiconductor fins.

6. The microelectronic device of claim 5 , wherein the first semiconductor fin includes source and drain regions of a conductivity type complementary to source and drain regions in the third semiconductor fin, and wherein the second semiconductor fin includes source and drain regions of a conductivity type complementary to source and drain regions of the fourth semiconductor.

7. A microelectronic device, comprising:
a plurality of gate electrode stripes disposed over a plurality of semiconductor fins each having a length greater than a width, wherein the length is the distance between ends of the fins, wherein each of the plurality of semiconductor fins consists essentially of silicon;
a plurality of isolation stripes substantially parallel to the plurality of gate electrode stripes and disposed between adjacent ones of the plurality of semiconductor fins, wherein the plurality of isolation stripes are self-aligned to the plurality of gate electrode stripes and between adjacent ends of the semiconductor fins, wherein the plurality of isolation stripes directly contact the adjacent ends of the semiconductor fins, wherein the adjacent ones of the plurality of semiconductor fins are bifurcated portions of a single semiconductor feature, wherein the adjacent semiconductor fins have longitudinal centerlines that are substantially coincident, and wherein surfaces of the gate electrode stripes facing away from surfaces of the semiconductor fins are substantially coplanar with surfaces of the isolation stripes, wherein the plurality of isolation stripes each have a transverse width that is no larger than a width of a gate stack that includes a gate electrode stripe of one of the plurality gate electrode stripes and a gate dielectric layer in contact with the gate electrode stripe, wherein the width of the gate electrode stripe is parallel along a same direction as the transverse width of each isolation stripe; and
a plurality of embedded epitaxial semiconductor regions in corresponding portions of the plurality of semiconductor fins between the plurality of gate electrode stripes and the plurality of isolation stripes, the plurality of embedded epitaxial semiconductor regions consisting essentially of silicon germanium.

8. The microelectronic device of claim 7 , wherein the plurality of gate electrode stripes and plurality of isolation stripes have a pitch that is an integer multiple of a minimum stripe pitch.

9. The microelectronic device of claim 7 , wherein the plurality of gate electrode stripes is interdigitated with the plurality of isolation stripes to form a population of stripes of a fixed pitch.

Assignees

• Bohr Mark T
• Cea Stephen M
• Chappell Barbara A
• Intel Corp

Inventors

• Bohr Mark T
• Cea Stephen M
• Chappell Barbara A

Classifications

• H10D84/853

  comprising FinFETs · CPC title

• H10D86/215

  comprising FinFETs · CPC title

• H10D86/011

  comprising FinFETs · CPC title

• H10D84/0193 Primary

  the components including FinFETs · CPC title

• H10D84/0158

  the components including FinFETs · CPC title