Ceramic electronic component and method for manufacturing ceramic electronic component

US11037729B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11037729-B2
Application numberUS-201916296541-A
CountryUS
Kind codeB2
Filing dateMar 8, 2019
Priority dateNov 2, 2016
Publication dateJun 15, 2021
Grant dateJun 15, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A ceramic electronic component that includes a plurality of ceramic layers which are stacked together, and an internal conductor layer disposed between two adjacent ceramic layers among the plurality of ceramic layers, and in which a ceramic layer that is adjacent to the internal conductor layer includes a plurality of pores.

First claim

Opening claim text (preview).

The invention claimed is: 1. A ceramic electronic component comprising: a plurality of ceramic layers which are stacked together; and an internal conductor layer disposed between two adjacent ceramic layers among the plurality of ceramic layers, wherein a ceramic layer among the plurality of ceramic layers that is adjacent to the internal conductor layer contains a plurality of pores, wherein each of the plurality of pores are each inside a shell layer, and wherein a resin is present inside the plurality of pores. 2. The ceramic electronic component according to claim 1 , wherein the shell layer is formed of an inorganic substance. 3. The ceramic electronic component according to claim 2 , wherein the inorganic substance contains at least SiO 2 . 4. The ceramic electronic component according to claim 2 , wherein the inorganic substance is at least one selected from the group consisting of SiO 2 , Al 2 O 3 , ZrO 2 , TiO 2 , and MgO. 5. The ceramic electronic component according to claim 2 , wherein the shell layer has a thickness of 0.03 μm to 0.5 μm. 6. The ceramic electronic component according to claim 1 , wherein the ceramic layer among the plurality of ceramic layers that is adjacent to the internal conductor layer has a porosity of 10% to 45%. 7. The ceramic electronic component according to claim 6 , wherein the porosity is 30% to 40%. 8. The ceramic electronic component according to claim 1 , wherein the ceramic layer contains a glass component. 9. The ceramic electronic component according to claim 8 , wherein the glass component does not contain boron. 10. The ceramic electronic component according to claim 8 , wherein the glass component has a softening point of 800° C. to 950° C. 11. The ceramic electronic component according to claim 8 , wherein the glass component has a softening point of 830° C. to 930° C. 12. The ceramic electronic component according to claim 8 , wherein the glass component contains, as main components thereof, 47% to 67% by weight of SiO 2 , 21% to 41% by weight of BaO, and 10% to 18% by weight of Al 2 O 3 . 13. A method for manufacturing a ceramic electronic component, the method comprising: mixing a ceramic powder, a pore-forming agent, a binder, a plasticizer, and a solvent to form a slurry, wherein the pore-forming agent has a core-shell structure including a core portion made of a resin bead which is not dissolved in the solvent and a shell layer which covers the circumference of the core portion and is formed of an inorganic substance; producing a green sheet from the slurry; forming an internal conductor layer having a conductive pattern on the green sheet; obtaining a green multilayer body by stacking and pressure-bonding a plurality of green sheets including the green sheet having the internal conductor layer formed thereon; and firing the green multilayer body so as to produce a plurality of ceramic layers which are stacked together, and the internal conductor layer is between two adjacent ceramic layers among the plurality of ceramic layers, wherein a ceramic layer among the plurality of ceramic layers that is adjacent to the internal conductor layer contains a plurality of pores, wherein each of the plurality of pores are each inside the shell layer, and wherein a resin is present inside the plurality of pores. 14. The method for manufacturing a ceramic electronic component according to claim 13 , wherein the inorganic substance is at least one selected from the group consisting of SiO 2 , Al 2 O 3 , ZrO 2 , TiO 2 , and MgO. 15. The method for manufacturing a ceramic electronic component according to claim 13 , wherein the shell layer has a thickness of 0.03 μm to 0.5 μm. 16. The method for manufacturing a ceramic electronic component according to claim 13 , wherein the resin bead contains at least one selected from acrylic resins, divinylbenzene resins, and polyimide resins. 17. The method for manufacturing a ceramic electronic component according to claim 13 , wherein the ceramic powder contains a glass component. 18. The method for manufacturing a ceramic electronic component according to claim 17 , wherein the glass component has a softening point of 800° C. to 950° C.

Assignees

Inventors

Classifications

  • B32B18/00Primary

    Layered products essentially comprising ceramics, e.g. refractory products · CPC title

  • Zirconium oxides, zirconates, hafnium oxides, hafnates, or oxide-forming salts thereof · CPC title

  • Forming laminates or joined articles comprising holes, channels or other types of openings · CPC title

  • Coatings characterised by their thickness · CPC title

  • characterised by the order of addition of constituents or additives · CPC title

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What does patent US11037729B2 cover?
A ceramic electronic component that includes a plurality of ceramic layers which are stacked together, and an internal conductor layer disposed between two adjacent ceramic layers among the plurality of ceramic layers, and in which a ceramic layer that is adjacent to the internal conductor layer includes a plurality of pores.
Who is the assignee on this patent?
Murata Manufacturing Co
What technology area does this patent fall under?
Primary CPC classification B32B18/00. Mapped technology areas include Operations & Transport.
When was this patent published?
Publication date Tue Jun 15 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).