Dual tap architecture for enabling secure access for DDR memory test controller

Patent metadata

Field	Value
Publication number	US-11037651-B2
Application number	US-201916675676-A
Country	US
Kind code	B2
Filing date	Nov 6, 2019
Priority date	Nov 7, 2018
Publication date	Jun 15, 2021
Grant date	Jun 15, 2021

Abstract

Disclosed are methods and apparatus for securely accessing and testing a double data rate (DDR) memory device. The apparatus includes a first memory test access port (TAP) configured to enable or disable access to at least one double date rate (DDR) memory device, a second memory TAP configured to enable or disable access to at least one non-DDR memory device, and a test controller configured to test the at least one DDR memory device via the first memory TAP or test the at least one non-DDR memory device via the second memory TAP. In an aspect, at least one non-DDR memory device contains proprietary information. Accordingly, access to the at least one non-DDR memory device via the second memory TAP is disabled when access to the at least one DDR memory device via the first memory TAP is enabled.

First claim

What is claimed is:

1. An apparatus for testing a memory device, comprising:
a first memory test access port (TAP) configured to enable or disable access to at least one double data rate (DDR) memory device;
a second memory TAP configured to enable or disable access to at least one non-DDR memory device; and
a test controller configured to test the at least one DDR memory device via the first memory TAP or test the at least one non-DDR memory device via the second memory TAP,
wherein access to the at least one non-DDR memory device via the second memory TAP is disabled when access to the at least one DDR memory device via the first memory TAP is enabled.

2. The apparatus of claim 1 , wherein the at least one DDR memory device is at least one Low Power DDR 4 (LPDDR4) memory device or Low Power DDR 5 (LPDDR5) memory device.

3. The apparatus of claim 1 , wherein the at least one non-DDR memory device contains proprietary information.

4. The apparatus of claim 1 , further comprising at least one fuse configured to enable or disable access to the first memory TAP.

5. The apparatus of claim 1 , wherein the at least one DDR memory device and the at least one non-DDR memory device are included in a same memory package.

6. The apparatus of claim 1 , further comprising a host incorporating the first memory TAP, the second memory TAP, and the test controller.

7. The apparatus of claim 6 , further comprising:
a communicative coupling configured to communicate signals for testing from the test controller to the at least one DDR memory device via the first memory TAP or the at least one non-DDR memory device via the second memory TAP.

8. The apparatus of claim 7 , further comprising one of a mobile phone or a mobile communicating device incorporating the host, the at least one DDR memory device, the at least one non-DDR memory device, and the communicative coupling.

9. A method for testing a memory device, comprising:
enabling or disabling access to at least one double data rate (DDR) memory device via a first memory test access port (TAP);
enabling or disabling access to at least one non-DDR memory device via a second memory TAP; and
testing, via a test controller, the at least one DDR memory device via the first memory TAP or the at least one non-DDR memory device via the second memory TAP,
wherein access to the at least one non-DDR memory device via the second memory TAP is disabled when access to the at least one DDR memory device via the first memory TAP is enabled.

10. The method of claim 9 , wherein the at least one DDR memory device is at least one Low Power DDR 4 (LPDDR4) memory device or Low Power DDR 5 (LPDDR5) memory device.

11. The method of claim 9 , wherein the at least one non-DDR memory device contains proprietary information.

12. The method of claim 9 , further comprising enabling or disabling access to the first memory TAP via at least one fuse.

13. The method of claim 9 , wherein the at least one DDR memory device and the at least one non-DDR memory device are included in a same memory package.

14. An apparatus for testing a memory device, comprising:
first access means for enabling or disabling access to at least one double data rate (DDR) memory device;
second access means for enabling or disabling access to at least one non-DDR memory device; and
test controlling means for testing the at least one DDR memory device via the first access means or the at least one non-DDR memory device via the second access means.

15. The apparatus of claim 14 , wherein the at least one DDR memory device is at least one Low Power DDR 4 (LPDDR4) memory device or Low Power DDR 5 (LPDDR5) memory device.

16. The apparatus of claim 14 , wherein the at least one non-DDR memory device contains proprietary information.

17. The apparatus of claim 14 , further comprising third access means for enabling or disabling access to the first access means.

18. The apparatus of claim 14 , wherein access to the at least one non-DDR memory device via the second access means is disabled when access to the at least one DDR memory device via the first access means is enabled.

19. The apparatus of claim 14 , wherein the at least one DDR memory device and the at least one non-DDR memory device are included in a same memory package.

20. A non-transitory computer-readable medium storing computer-executable code, comprising code for causing a computer to:
enable or disable access to at least one double data rate (DDR) memory device via a first memory test access port (TAP);
enable or disable access to at least one non-DDR memory device via a second memory TAP; and
test, via a test controller, the at least one DDR memory device via the first memory TAP or the at least one non-DDR memory device via the second memory TAP,
wherein access to the at least one non-DDR memory device via the second memory TAP is disabled when access to the at least one DDR memory device via the first memory TAP is enabled.

21. The non-transitory computer-readable medium of claim 20 , wherein the at least one DDR memory device is at least one Low Power DDR 4 (LPDDR4) memory device or Low Power DDR 5 (LPDDR5) memory device.

22. The non-transitory computer-readable medium of claim 20 , wherein the at least one non-DDR memory device contains proprietary information.

23. The non-transitory computer-readable medium of claim 20 , further comprising code for causing the computer to enable or disable access to the first memory TAP via at least one fuse.

24. The non-transitory computer-readable medium of claim 20 , wherein the at least one DDR memory device and the at least one non-DDR memory device are included in a same memory package.

Assignees

• Qualcomm Inc

Inventors

• Jain Arvind
• George Anju
• Pattnaik Swayam

Classifications

• G11C5/025

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title

• G11C29/56 Primary

  External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor · CPC title

• G11C2029/5602

  Interface to device under test · CPC title

• G11C29/48

  Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths · CPC title

• G11C29/14

  Implementation of control logic, e.g. test mode decoders · CPC title