Non-volatile memory controller cache architecture with support for separation of data streams

Patent metadata

Field	Value
Publication number	US-11036637-B2
Application number	US-201916418880-A
Country	US
Kind code	B2
Filing date	May 21, 2019
Priority date	Dec 19, 2014
Publication date	Jun 15, 2021
Grant date	Jun 15, 2021

Abstract

A computer-implemented method, according to one embodiment, includes: retrieving a physical block address corresponding to a logic block address, extracting information from the physical block address, and performing a lookup operation in cache using the extracted information. A range check of the physical block address is further performed in response to the lookup operation succeeding, while data is read from the cache in response to the range check succeeding. An architecture of the cache supports separation of data streams, as well as parallel writes to different non-volatile memory channels. The cache architecture further supports pipelining of the parallel writes to different non-volatile memory planes. Moreover, the non-volatile memory controller is configured to perform a direct memory lookup in the cache based on a physical block address.

First claim

What is claimed is:

1. A computer-implemented method, comprising:
retrieving a physical block address corresponding to a logic block address;
extracting information from the physical block address;
performing a lookup operation in cache using the extracted information;
performing a range check of the physical block address in response to the lookup operation succeeding; and
reading data from the cache in response to the range check succeeding,
wherein an architecture of the cache supports separation of data streams,
wherein the cache architecture supports parallel writes to different non-volatile memory channels,
wherein the cache architecture supports pipelining of the parallel writes to different non-volatile memory planes,
wherein the non-volatile memory controller is configured to perform a direct memory lookup in the cache based on a physical block address.

2. The computer-implemented method of claim 1 , comprising:
receiving a logical block address write request;
retrieving a previous physical block address and heat value associated with the logical block address from memory;
incrementing the heat value;
computing a stream for the logic block address based on the incremented heat value;
incrementing a fill pointer of the stream;
writing data of the logic block address write request to a page indexed by the incremented fill pointer; and
retrieving an updated physical block address of the page indexed by the incremented fill pointer,
wherein writing data to the page indexed by the incremented fill pointer is delayed when the fill pointer cannot be incremented.

3. The computer-implemented method of claim 2 , comprising:
updating a logical to physical table with the updated physical block address; and
invalidating the previous physical block address.

4. The computer-implemented method of claim 1 , wherein the extracted information includes a type of information selected from the group consisting of: a stream, a plane, a channel and a block associated with the physical block address.

5. The computer-implemented method of claim 1 , wherein performing the range check includes:
using a valid pointer and a fill pointer of the stream to determine whether the data is located in cache; and
determining a current write count of the cache,
wherein reading the data from the cache is delayed when the write count exceeds a threshold value.

6. The computer-implemented method of claim 1 , comprising:
reading the data from non-volatile memory in response to the range check failing; and
reading the data from non-volatile memory in response to the lookup operation failing.

7. The computer-implemented method as recited in claim 1 , wherein the non-volatile memory includes NAND Flash memory.

8. A computer-implemented method, comprising:
performing a direct memory lookup in cache based on a physical block address,
wherein performing the direct memory lookup in cache includes:
receiving a physical block address corresponding to a logic block address,
extracting information from the physical block address, and
performing a lookup operation in cache using the extracted information.

9. The computer-implemented method of claim 8 , wherein performing the direct memory lookup in cache includes:
performing a range check of the physical block address in response to the lookup operation succeeding;
reading data from cache in response to the range check succeeding; and
reading the data from non-volatile memory in response to the range check failing.

10. The computer-implemented method of claim 9 , wherein the extracted information includes a type of information selected from the group consisting of: a stream, a plane, a channel and a block associated with the physical block address.

11. The computer-implemented method of claim 9 , wherein performing the range check includes:
using a valid pointer and a fill pointer of the stream to determine whether the data is located in cache; and
determining a current write count of the cache,
wherein reading the data from the cache is delayed when the write count exceeds a threshold value.

12. The computer-implemented method of claim 9 , wherein the extracted information includes a type of information selected from the group consisting of: a stream, a plane, a channel and a block associated with the physical block address wherein performing the direct memory lookup in cache includes:
read the data from non-volatile memory in response to the lookup operation failing.

13. The computer-implemented method of claim 9 , wherein the non-volatile memory includes NAND Flash memory.

14. The computer-implemented method of claim 8 , comprising:
receiving a logic block address write request;
retrieving a previous physical block address and heat value associated with the logical block address from memory;
incrementing the heat value;
computing, by the non-volatile memory controller, a stream for the logic block address based on the incremented heat value;
incrementing a fill pointer of the stream;
writing data of the logic block address write request to a page indexed by the incremented fill pointer; and
retrieving an updated physical block address of the page indexed by the incremented fill pointer.

15. The computer-implemented method of claim 14 , comprising:
updating a logical to physical table with the updated physical block address; and
invalidating the previous physical block address.

16. The computer-implemented method of claim 14 , wherein writing data to the page indexed by the incremented fill pointer is delayed when the fill pointer cannot be incremented.

17. A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions readable and/or executable by a controller to cause the controller to:
perform, by the controller, a direct memory lookup in cache based on a physical block address,
wherein performing the direct memory lookup in cache includes:
receiving a physical block address corresponding to a logic block address,
extracting information from the physical block address, and
performing a lookup operation in cache using the extracted information.

18. The computer program product of claim 17 , wherein performing the direct memory lookup in cache includes:
performing a range check of the physical block address in response to the lookup operation succeeding;
reading data from cache in response to the range check succeeding; and
reading the data from non-volatile memory in response to the range check failing.

19. The computer program product of claim 18 , wherein the extracted information includes a type of information selected from the group consisting of: a stream, a plane, a channel and a block associated with the physical block address.

20. The computer program product of claim 18 , wherein performing the range check includes:
using a valid pointer and a fill pointer of the stream to determine whether the data is located in cache; and
determining a current write count of the cache,
wherein reading the data from the cache is delayed when the write count exceeds a threshold value.

Assignees

• IBM

Inventors

• Camp Charles J
• Fisher Timothy J
• Fry Aaron D
• Ioannou Nikolas
• Koltsidas Ioannis
• Pletka Roman
• Tomic Sasa
• Walls Andrew D

Classifications

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G06F2212/7202

  Allocation control and policies · CPC title

• G06F2212/222

  Non-volatile memory · CPC title

• G06F2212/7208

  Multiple device management, e.g. distributing data over multiple flash devices · CPC title

• G06F2212/1016

  Performance improvement · CPC title