Enhanced shutter efficiency time-of-flight pixel

Patent metadata

Field	Value
Publication number	US-11032496-B2
Application number	US-201916517904-A
Country	US
Kind code	B2
Filing date	Jul 22, 2019
Priority date	Jul 22, 2019
Publication date	Jun 8, 2021
Grant date	Jun 8, 2021

Abstract

A time-of-flight pixel array comprises multiple pixel cells. The pixel cell comprises a light collection region, a light shielded region, and a deep trench isolation (DTI) structure that encircles the light collection region to prevent light from entering the light shielded region. Photogate in the light collection region is disposed above a photodiode to accumulate the photo-generated electrical charges. A doped region disposed near the photogate collects the attracted charges. The doped region extends to the light shielded region and transfers the collected charges to a floating diffusion through a shutter transistor also in the light shielded region. DTI or similar structures are deployed to the entire pixel array to prevent light from exchanging between different light collection regions and light from entering the light shielded regions of all pixel cells. Interference between the shielded regions of different pixel cells is also minimized.

First claim

What is claimed is:

1. A time-of-flight (TOF) pixel array, comprising:
a pixel cell, wherein the pixel cell comprises a first cell region, a second cell region, and a deep trench isolation (DTI) structure,
wherein the first cell, region comprises
a photodiode disposed in a semiconductor material layer to accumulate image charges in response to light incident upon the photodiode,
a first photogate disposed proximate to a frontside of the semiconductor material layer and positioned above the photodiode to attract charges in the semiconductor material layer toward the frontside in response to a Voltage applied to the first photogate, and
a first doped region disposed proximate to the frontside of the semiconductor material layer, wherein the first doped region is implanted partially underneath the first photogate to accumulate charges of the photodiode when the voltage is applied to the first photogate,

wherein the second cell region comprises
a second doped region disposed proximate to the frontside of the semiconductor material layer,
a floating diffusion (FD) disposed in the semiconductor material layer proximate to the frontside of the semiconductor material layer,
a shutter transistor disposed proximate to the frontside of the semiconductor material layer, wherein a source terminal of the shutter transistor is coupled to the second doped region, wherein a drain terminal of the shutter transistor is coupled to the FD, and wherein a gate terminal of the shutter transistor is configured to transfer the image charges in the second doped region to the FD in response to a shutter signal, and

wherein the DTI structure is disposed in the semiconductor material layer to laterally encircle the first cell region.

2. The TOF pixel array of claim 1 , further comprising a metal jumper coupled between the first doped region and the second doped region.

3. The TOF pixel array of claim 1 , further comprising an oxide layer disposed between the semiconductor material layer and the first photogate, and between the semiconductor material layer and the gate terminal of the shutter transistor.

4. The TOF pixel array of claim 1 , wherein the second cell region further comprises a reset transistor disposed proximate to the frontside of the semiconductor material layer, wherein a source terminal of the reset transistor is coupled to the second doped region, and wherein an oxide layer is disposed between the semiconductor material layer and the gate terminal of the reset transistor.

5. The TOF pixel array of claim 1 , wherein the second cell region further comprises a source follower (SF) transistor disposed proximate to the frontside of the semiconductor material layer, and wherein a gate terminal of the SF transistor is coupled to the FD, and wherein an oxide layer is disposed between the semiconductor material layer and the gate terminal of the SF transistor.

6. The TOF pixel array of claim 1 , wherein the first photogate in the pixel cell is one of polysilicon, doped polysilicon, and metal, and wherein the gate of the shutter transistor in the pixel cell is one of polysilicon, doped polysilicon, and metal.

7. The TOF pixel array of claim 1 , wherein the first cell region comprises a plurality of first doped regions, wherein the first photogate comprises a plurality of photogate fingers, and wherein one ends of the photogate fingers are positioned partially above the first doped regions.

8. The TOF pixel array of claim 7 , wherein the first doped regions are interconnected to each other by a metal stripe.

9. The TOF pixel array of claim 7 , wherein the pixel cell includes the first photogate and a second photogate and a first and second readout circuits, wherein each one of the first and second readout circuits comprises the reset transistor, the shutter transistor, the FD, and the SF transistor.

10. The TOF pixel array of claim 9 , wherein the pixel cell comprises the first readout circuit disposed laterally alongside a first wall of the four outer walls encircling the DTI structure and the second readout circuit is disposed laterally, alongside a second wall of the four outer walls encircling the DTI structure, which is perpendicular to the first wall.

11. The TOF pixel array of claim 9 , wherein the pixel cell comprises the first readout circuit disposed laterally alongside a first wall of the four outer walls encircling the DTI structure and the second readout circuit is disposed laterally alongside a second wall of the four outer walls encircling the DTI structure, which is parallel to the first wall.

12. The TOF pixel array of claim 1 , further comprising a plurality of row pixel-separation DTIs and a plurality of column pixel-separation DTIs, wherein the pixel cell is encircled by the two row pixel-separation DTIs and two column pixel-separation DTIs.

13. The TOF pixel array of claim 1 , further comprising a plurality of row shallow trench isolations (STIs) and a plurality of column STIs, wherein the pixel cell is encircled by the two row STIs and two column STIs.

14. The TOF pixel array of claim 1 , wherein the first doped region and the second doped region are strongly doped n-type regions that are conductive.

15. A time-of-flight (TOF) light sensing system, comprising:
a light source to emit light to an object;
a pixel array optically coupled to sense the emitted light that is reflected from the object,
wherein the pixel array comprises a pixel cell, wherein the pixel cell comprises a first cell region, a second cell region, and a deep trench isolation (DTI) structure,
wherein the first cell region comprises
a photodiode disposed in a semiconductor material layer to accumulate image charges in response to tight incident upon the photodiode,
a first photogate disposed proximate to a frontside of the semiconductor material layer and positioned above the photodiode to attract charges in the semiconductor material layer toward the frontside in response to a voltage applied to the first photogate, and
a first doped region disposed proximate to the frontside of the semiconductor material layer, wherein the first doped region is implanted partially underneath the first photogate to accumulate charges of the photodiode when the voltage is applied to the first photogate,

wherein the second cell region comprises
a second doped region disposed proximate to the frontside of the semiconductor material layer,
a floating diffusion (FD) disposed in the semiconductor material layer proximate to the frontside of the semiconductor material layer,
a shutter transistor disposed proximate to the frontside of the semiconductor material layer, wherein a source terminal of the shutter transistor is coupled to the second doped region, wherein a drain terminal of the shutter transistor is coupled to the FD, and wherein a gate terminal of the shutter transistor is configured to transfer the image charges n the second doped region to the FD in response to a shatter signal, and

wherein the DTI structure is disposed in the semiconductor mat layer to laterally encircle the first cell region; and

control circuitry coupled to control the light source and the pixel array to sense the emitted light that is reflected from the object to the pixel array.

16. The TOF light, sensing system of claim 15 , further comprising a metal jumper coupled between the first doped region acid the second doped region.

17. The TOF light sensing system of claim 15 , further comprising an oxide layer disposed between the semiconductor material layer and the photogate, and between the semiconductor material layer and the

Assignees

• Omnivision Tech Inc

Inventors

• Webster Eric

Classifications

• H04N25/59 Primary

  by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance · CPC title

• H04N25/78

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title

• H10F39/80373

  characterised by the gate of the transistor · CPC title

• H10F39/8057

  Optical shielding · CPC title

• H10F39/811

  Interconnections · CPC title