Carrier aggregated signal transmission and reception

Patent metadata

Field	Value
Publication number	US-11031962-B2
Application number	US-202016779763-A
Country	US
Kind code	B2
Filing date	Feb 3, 2020
Priority date	Dec 5, 2017
Publication date	Jun 8, 2021
Grant date	Jun 8, 2021

Abstract

Provided are a radio-frequency integrated chip (RFIC) and a wireless communication device including the RFIC. An RFIC configured to receive a carrier aggregated receive signal having at least first and second carrier signals may include first and second carrier receivers configured to generate, from the receive signal, first and second digital carrier signals, respectively. A phase-locked loop (PLL) may output a first frequency signal having a first frequency to the first carrier receiver and the second carrier receiver. The first and second carrier receivers may include first and second analog mixers, respectively, for translating frequencies of the receive signal, using the first frequency signal and the second frequency signal, respectively. Each of the first and second carrier receivers may further include a digital mixer for further translating the frequencies of the receive signal in the digital domain.

First claim

What is claimed is:

1. A radio-frequency integrated chip configured to receive a receiving signal, the radio-frequency integrated chip comprising:
a signal divider that divides the receiving signal into at least a first receiving signal and a second receiving signal;
a first analog receiving circuit configured to receive the first receiving signal, translate frequencies of the first receiving signal in an analog domain and thereby generate a first analog receiving signal;
a first analog-to-digital converter (ADC) configured to analog-to-digital convert the first analog receiving signal and thereby generate a first digital receiving signal;
a phase-locked loop (PLL) configured to output a first frequency signal having a first frequency;
a first frequency divider configured to divide the first frequency signal and thereby generate a second frequency signal having a second frequency, and output the generated second frequency signal to the first analog receiving circuit;
a second frequency divider configured to divide the first frequency signal and thereby generate a third frequency signal having a third frequency, and output the generated third frequency signal to the first ADC;
a second analog receiving circuit that receives the second receiving signal; and
a third frequency divider configured to divide the first frequency signal and thereby generate a fourth frequency signal having a fourth frequency, and output the generated fourth frequency signal to the second analog receiving circuit;
wherein the first analog receiving circuit translates the frequencies of the first receiving signal based on the second frequency signal and the second analog receiving circuit translates the frequencies of the second receiving signal based on the fourth frequency signal.

2. The radio-frequency integrated chip of claim 1 , further comprising:
a first digital receiving circuit configured to receive the first digital receiving signal, down-convert frequencies of the first digital receiving signal, and thereby generate and output a first digital carrier signal.

3. The radio-frequency integrated chip of claim 1 , wherein the first ADC is configured to provide the first digital receiving signal to a modulator-demodulator (MODEM), wherein the MODEM generates a digital carrier signal based on the first digital receiving signal.

4. The radio-frequency integrated chip of claim 1 , wherein the receiving signal is composed of at least first and second carrier signals, and further comprising:
a first carrier receiver comprising the first analog receiving circuit, and a first digital receiving circuit configured to further translate frequencies of the first carrier signal in a digital domain and output a first digital carrier signal corresponding to the first carrier signal, and
a second carrier receiver comprising the second analog receiving circuit, and a second digital receiving circuit configured to further translate frequencies of the second carrier signal in the digital domain and output a second digital carrier signal corresponding to the second carrier signal.

5. The radio-frequency integrated chip of claim 4 , wherein the first analog receiving circuit comprises a first analog mixer, and the first carrier receiver further comprises the first frequency divider, which outputs the generated second frequency signal to the first analog mixer,
the second analog receiving circuit comprises a second analog mixer, and the second carrier receiver further comprises the third frequency divider, which outputs the generated fourth frequency signal to the second analog mixer, and
the first analog mixer down-converts frequencies of the first receiving signal based on the second frequency signal and generates a first mixed receiving signal, and the second analog mixer down-converts the frequencies of the second receiving signal based on the fourth frequency signal and generates a second mixed receiving signal.

6. The radio-frequency integrated chip of claim 5 , wherein the first carrier receiver further comprises a fourth frequency divider configured to divide the first frequency signal and generate a fifth frequency signal having a fifth frequency different from the second frequency, wherein the second frequency signal or the fifth frequency signal is outputted from the first frequency divider or the fourth frequency divider, respectively, to the first analog receiving circuit based on a first frequency selection signal, and
the second carrier receiver further comprises a sixth frequency divider configured to divide the first frequency signal and generate a sixth frequency signal having a sixth frequency different from the fourth frequency, wherein the fourth frequency signal or the sixth frequency signal is outputted from the second frequency divider or the sixth frequency divider, respectively, to the second analog receiving circuit based on a second frequency selection signal.

7. The radio-frequency integrated chip of claim 5 , wherein the first carrier receiver further comprises a first analog filter configured to filter the first mixed receiving signal outside a first predetermined band and generate the first analog receiving signal, and
the second carrier receiver further comprises a second analog filter configured to filter a second mixed receiving signal outside a second predetermined band and generate a second analog receiving signal.

8. The radio-frequency integrated chip of claim 7 , wherein the first carrier receiver comprises the first ADC, and
the second carrier receiver further comprises a second ADC configured to analog-to-digital convert the second analog receiving signal and thereby generate a second digital receiving signal.

9. The radio-frequency integrated chip of claim 8 , wherein at least one of the first ADC and the second ADC samples the first analog receiving signal or the second analog receiving signal based on a frequency signal generated by dividing the first frequency signal received from the PLL, to generate the first digital receiving signal or the second digital receiving signal.

10. The radio-frequency integrated chip of claim 8 , wherein
the second carrier receiver further comprises a fourth frequency divider configured to divide the first frequency signal, generate a fifth frequency signal having a fifth frequency, and output the generated fifth frequency signal to the second ADC, and
the first ADC generates the first digital receiving signal based on the third frequency signal, and the second ADC generates the second digital receiving signal based on the fifth frequency signal.

11. The radio-frequency integrated chip of claim 5 , further comprising:
a first digital receiving mixer configured to receive the first digital receiving signal, down-convert frequencies of the first digital receiving signal, and thereby generate and output the first digital carrier signal, and
a second digital receiving mixer configured to receive the second digital receiving signal, down-convert frequencies of the second digital receiving signal, and thereby generate and output the second digital carrier signal,
wherein the first analog mixer down-converts frequencies of the first receiving signal and thereby generates a first mixed receiving signal, the second analog mixer down-converts frequencies of the second receiving signal and thereby generates a second mixed receiving signal,
the first carrier receiver comprises the first ADC, which is configured to generate the first digital receiving signal based on the first mixed receiving signal, and the first carrier receiver further comprises a first digital receiving filter configured to filter the first digital receiving signal outside a first predet

Assignees

• Samsung Electronics Co Ltd

Inventors

• Oh Seung-Hyun
• Lo Chilun
• Sung Barosaim
• Lee Jae-Hoon
• Lee Jong-Woo

Classifications

• H04B1/0053 Primary

  with common antenna for more than one band · CPC title

• H04B1/0057 Primary

  using diplexing or multiplexing filters for selecting the desired band · CPC title

• H04L5/001

  the frequencies being arranged in component carriers · CPC title

• H03L7/16

  Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop · CPC title

• H03L7/08

  Details of the phase-locked loop · CPC title