Conversion and folding circuit for delay-based analog-to-digital converter system

Patent metadata

Field	Value
Publication number	US-11031947-B2
Application number	US-202016860334-A
Country	US
Kind code	B2
Filing date	Apr 28, 2020
Priority date	Dec 31, 2018
Publication date	Jun 8, 2021
Grant date	Jun 8, 2021

Abstract

An RF receiver including: a low noise amplifier adapted to be coupled to an antenna and having an output; a bandpass filter coupled to the output of the low noise amplifier and having a voltage signal output, VIN; a conversion and folding circuit; and an analog-to-digital converter for converting the earlier-arriving or later-arriving delay signals into a digital code representing the voltage signal. The conversion and folding circuit including: a voltage-to-delay converter block, including preamplifiers, for converting the voltage signal into delay signals; and a folding block, including logic gates coupled to the preamplifiers, for selecting earlier-arriving and later-arriving ones of the delay signals.

First claim

What is claimed as new and desired to be protected by Letters Patent of the United States is:

1. An RF receiver comprising:
a low noise amplifier adapted to be coupled to an antenna and having an output;
a bandpass filter coupled to the output of the low noise amplifier and having a voltage signal output, V IN ;
a conversion and folding circuit including:
a voltage-to-delay converter block, including preamplifiers, for converting the voltage signal into delay signals; and
a folding block, including logic gates coupled to the preamplifiers, for selecting earlier-arriving and later-arriving ones of the delay signals; and

an analog-to-digital converter for converting the earlier-arriving or later-arriving delay signals into a digital code representing the voltage signal.

2. The RF receiver of claim 1 , wherein the logic gates include first gates for selecting earlier-arriving signals from the preamplifiers, and a second gate for selecting a latest-arriving signal from the first gates, wherein the first and second gates are coupled to the preamplifiers.

3. The RF receiver of claim 1 , wherein the folding block includes multiple chains of logic gates, and wherein the folding circuit is configured to select a smallest delay signal from one of the chains of logic gates, without receiving a select signal from outside of the folding block.

4. The RF receiver of claim 2 , wherein the folding block includes an odd chain and an even chain, wherein the odd chain includes the first gates and the second gate, wherein the even chain includes third gates for selecting earlier-arriving signals from the preamplifiers, and a fourth gate for selecting a latest-arriving signal from the third gates, wherein the preamplifiers include adjacent preamplifiers, and wherein the odd chain receives delay signals from a first one of the adjacent preamplifiers, and the even chain receives delay signals from a second one of the adjacent preamplifiers.

5. The RF receiver of claim 2 , wherein the folding block includes a first chain and a second chain, wherein the first chain includes the first gates and the second gate, and wherein the second chain includes third gates, coupled to the first gates, for selecting earlier-arriving signals associated with adjacent ones of the preamplifiers, and a fourth gate for selecting a latest-arriving signal from the third gates.

6. The RF receiver of claim 5 , wherein the first chain includes AND gates for selecting later-arriving signals from the preamplifiers, and an OR gate for selecting an earliest-arriving signal from the AND gates, wherein the OR gate is coupled to the AND gates, and wherein the second chain includes the AND gates and the OR gate.

7. The RF receiver of claim 6 , further comprising a chain selection circuit for selecting one of the first and second chains, and wherein the chain selection circuit includes first and second comparators.

8. The RF receiver of claim 7 , wherein the chain selection circuit is coupled to the first and second chains, and causes an output of the second chain to be transmitted to an analog-to-digital converter when outputs of the first and second comparators do not match.

9. An analog-to-digital converter system having a voltage signal, V IN , input, the analog-to-digital converter system comprising:
a conversion and folding circuit including:
preamplifiers for converting the voltage signal into delay signals; and
logic gates for receiving the delay signals from the preamplifiers, the logic gates include first gates for selecting earlier-arriving signals from the preamplifiers, and a second gate for selecting a latest-arriving signal from the first gates, wherein each one of the first gates is coupled to a respective one of the preamplifiers, and wherein the second gate is coupled to the first gates; and
wherein the logic gates further include AND gates for selecting later-arriving signals from the preamplifiers, and an OR gate for selecting an earliest-arriving signal from the AND gates, wherein the OR gate is coupled to the AND gates; and

an analog-to-digital converter coupled to the conversion and folding circuit and operable to convert the later-arriving signals or the earliest-arriving signal to a digital code representative of the voltage signal.

10. The analog-to-digital converter system of claim 9 , further comprising an odd chain and an even chain, wherein the odd chain includes the first gates and the second gate, wherein the even chain includes third gates for selecting earlier-arriving signals from the preamplifiers, and a fourth gate for selecting a latest-arriving signal from the third gates, wherein the preamplifiers include adjacent preamplifiers, and wherein the odd chain receives delay signals from a first one of the adjacent preamplifiers, and the even chain receives delay signals from a second one of the adjacent preamplifiers.

11. The system analog-to-digital converter system of claim 9 , wherein the logic gates include a first chain and a second chain, wherein the first chain includes the first gates, the second gate, the AND gates, and the OR gate, and wherein the second chain includes the AND gates, the OR gate, third gates, coupled to the first gates, for selecting earlier-arriving signals from adjacent ones of the first gates, and a fourth gate for selecting a latest-arriving signal from the third gates.

12. The analog-to-digital converter system of claim 11 , further comprising a chain selection circuit for selectively transmitting an output of one of the first and second chains to an analog-to-digital converter.

13. The analog-to-digital converter system of claim 11 , further comprising a processor coupled to the analog-to-digital converter.

Assignees

• Texas Instruments Inc

Inventors

• Dusad Shagun
• Shetty Chirag Chandrahas
• Pentakota Visvesvaraya Appala

Classifications

• H03M1/50 Primary

  with intermediate conversion to time interval (H03M1/64 takes precedence) · CPC title

• H03M1/365

  the voltage divider being a single resistor string · CPC title

• H03M1/204

  in which one or more virtual intermediate reference signals are generated between adjacent original reference signals, e.g. by connecting pre-amplifier outputs to multiple comparators · CPC title

• H03M1/445

  the stages being of the folding type · CPC title

• H03M1/141

  in which at least one step is of the folding type; Folding stages therefore · CPC title