Dual electro-mechanical oscillator for dynamically reprogrammable logic gate

Patent metadata

Field	Value
Publication number	US-11031937-B2
Application number	US-201816606436-A
Country	US
Kind code	B2
Filing date	Apr 17, 2018
Priority date	Apr 19, 2017
Publication date	Jun 8, 2021
Grant date	Jun 8, 2021

Abstract

Embodiments include a logic gate system comprising a first micro-cantilever beam arranged in parallel to a second micro-cantilever beam in which a length of the first micro-cantilever beam is shorter than a length of the second micro-cantilever beam. The first micro-cantilever beam is adjacent to the second micro-cantilever beam and the first micro-cantilever beam is coupled to an input DC bias voltage source to the logic gate system. The second micro-cantilever beam is coupled to an input AC voltage signal that dynamically sets a logic operation of the logic gate system by at least changing an operating resonance frequency for one or more of the first micro-cantilever beam and the second micro-cantilever beam.

First claim

Therefore, at least the following is claimed:

1. A logic gate system comprising:
a first micro-cantilever beam arranged in parallel to a second micro-cantilever beam, wherein a length of the first micro-cantilever beam is different than a length of the second micro-cantilever beam, wherein the first micro-cantilever beam is adjacent to the second micro-cantilever beam,
wherein the first micro-cantilever beam is coupled to an input DC bias voltage source to the logic gate system, and the second micro-cantilever beam is coupled to an input AC voltage signal that dynamically sets a logic operation of the logic gate system by at least changing an operating resonance frequency for one or more of the first micro-cantilever beam and the second micro-cantilever beam.

2. The logic gate system of claim 1 , wherein the logic operation of the logic gate system is configurable to operate as either a first AND logic gate at a first operating frequency of the input AC voltage signal, a second AND logic gate at a second operating frequency of the input AC voltage signal, or an XOR logic gate at a third operating frequency of the input AC voltage signal.

3. The system of claim 2 , wherein the XOR logic gate and the first AND logic gate or the second AND logic gate collectively operate as a HALF ADDER circuit.

4. The system of claim 1 , wherein resonating state of at least one of the first and second micro-cantilever beams represents a logic ON/1 output, and wherein a non-resonating state of at least one of the first and second micro-cantilever beams represents a logic OFF/0 output.

5. The logic gate system of claim 1 , wherein the second micro-cantilever beam is coupled to a DC gate bias signal, and wherein the DC gate bias signal is adjustable to represent an input value of the logic gate system.

6. The system of claim 1 , wherein the logic operation of the logic gate system is selectively operable as each of a 1-bit NOT logic gate, a 2-bit NOR logic gate, a 3-bit NOR logic gate, a 2-bit XOR logic gate, a 2-bit AND logic gate, and a 3-bit AND logic gate as selected by tuning an operating frequency of the input AC voltage signal to a designated frequency corresponding to a particular logic gate.

7. A method of implementing a logic gate system, comprising:
providing a first micro-cantilever beam arranged in parallel with a second micro-cantilever beam, wherein a length of the first micro-cantilever beam is different than a length of the second micro-cantilever beam and wherein the first micro-cantilever beam is adjacent to the second micro-cantilever beam;
connecting the first micro-cantilever beam to an input DC bias voltage source for the logic gate system;
connecting the second micro-cantilever beam to an input AC voltage signal;
dynamically setting a logic operation of the logic gate system by at least changing an operating resonance frequency for the first micro-cantilever beam or the second micro-cantilever beam or both;
inputting an input bit signal to the logic gate system; and
obtaining an output bit representation for the logic gate system from a first fixed electrode.

8. The method of claim 7 , further comprising:
configuring the logic operation of the logic gate system to operate as either a first AND logic gate at a first operating frequency of the input AC voltage signal, a second AND logic gate at a second operating frequency of the input AC voltage signal, or an XOR logic gate at a third operating frequency of the input AC voltage signal, wherein the input DC bias voltage represents an input bit signal to the logic gate system.

9. The method of claim 8 , wherein the XOR logic gate and the first AND logic gate or the second AND logic gate collectively operate as a HALF ADDER circuit.

10. The method of claim 7 , wherein a resonating state of at least one of the first and second micro-cantilever beams represents a logic ON/1 output, and wherein a non-resonating state of at least one of the first and second micro-cantilever beams represents a logic OFF/0 output.

11. The method of claim 7 , wherein the second micro-cantilever beam is coupled to a DC gate bias signal, and wherein the DC gate bias signal is adjustable to represent an input value of the logic gate system.

12. The method of claim 7 , wherein the logic operation of the logic gate system is configured to operate as each of a 1-bit NOT logic gate, a 2-bit NOR logic gate, a 3-bit NOR logic gate, a 2-bit XOR logic gate, a 2-bit AND logic gate, and a 3-bit AND logic gate as selected by tuning an operating frequency of the input AC voltage signal to a designated frequency corresponding to a particular logic gate.

13. A method of operating a logic gate, comprising:
applying a DC-bias voltage to a first micro-cantilever;
applying an AC voltage signal to a second micro-cantilever arranged in parallel and adjacent to the first cantilever, wherein a frequency of the AC voltage signal sets a logic operation of the logic gate, wherein applying the AC voltage signal with a first frequency to the second micro-cantilever causes the logic gate to operate according to a first logic operation, and wherein applying the AC voltage signal with a second frequency different than the first frequency causes the logic gate to operate according to a second logic operation different than the first logic operation;
applying a gate DC-bias voltage to the second micro-cantilever, wherein the gate DC-bias signal represents a logic input to the logic gate; and
determining, based on whether at least one of the first and second micro-cantilevers vibrate at a resonant frequency in response to the frequency of the AC voltage signal and the gate DC-bias voltage, an output of the logic gate.

14. The method of claim 13 , wherein applying the gate DC-bias voltage to the second micro-cantilever comprises:
applying a first discrete DC voltage level to represent a first input value; and
applying a second discrete DC voltage to represent a second input value different than the first input value.

15. The method of claim 13 , wherein the first micro-cantilever is shorter than the second micro-cantilever.

16. The method of claim 13 , wherein the second micro-cantilever is shorter than the first micro-cantilever.

17. The method of claim 13 , further comprising:
configuring, based on a frequency of the AC voltage signal, the logic operation of the logic gate system to operate as either a first AND logic gate at a first operating frequency of the AC voltage signal, a second AND logic gate at a second operating frequency of the AC voltage signal, or an XOR logic gate at a third operating frequency of the AC voltage signal, wherein the gate DC bias voltage represents an input bit signal to the logic gate system.

18. The method of claim 13 , further comprising:
configuring the logic operation of the logic gate system to operate as each of a 1-bit NOT logic gate, a 2-bit NOR logic gate, a 3-bit NOR logic gate, a 2-bit XOR logic gate, a 2-bit AND logic gate, and a 3-bit AND logic gate by tuning the frequency of the AC voltage signal to a designated frequency corresponding to a particular logic gate.

19. The method of claim 13 , further comprising:
using the determined output of the logic gate as part of a mechanical computer.

Assignees

• Univ King Abdullah Sci & Tech

Inventors

• Nanaiah Karumbaiah Chappanda
• Younis Mohammad Ibrahim

Classifications

• H03K19/21 Primary

  EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical · CPC title

• H03H3/0072

  of microelectro-mechanical resonators or networks (micromembranes or microbeams B81B2203/01; manufacture of microstructural devices in general B81C) · CPC title

• H03K19/02 Primary

  using specified components ({H03K19/0005 - H03K19/0021}, H03K19/003 - H03K19/0175 take precedence) · CPC title

• H03H9/02409

  by application of a DC-bias voltage (H03H9/02417 takes precedence) · CPC title

• H03H9/2457

  Clamped-free beam resonators · CPC title