Method for generating a bias current for biasing a differential pair of transistors and corresponding integrated circuit

Patent metadata

Field	Value
Publication number	US-11031917-B2
Application number	US-201916425437-A
Country	US
Kind code	B2
Filing date	May 29, 2019
Priority date	Jun 1, 2018
Publication date	Jun 8, 2021
Grant date	Jun 8, 2021

Abstract

An operational amplifier integrated circuit includes a differential pair of transistors having a first input, a second input. A bias current generator applies a bias current to an output of the differential pair of transistors. A control loop generates a control voltage arising from a difference in potentials between the first input and the second input. An additional current that is added to the bias current is generated in response to the control voltage.

First claim

The invention claimed is:

1. A method for generating a bias current for biasing a differential pair of transistors which include a first input, a second input, a first intermediate output, a second intermediate output, the method comprising:
generating a bias current for biasing the first intermediate output and the second intermediate output;
generating a control voltage arising from a difference in potentials between a potential on the first input and a potential on a node receiving the bias current; and
generating in response to the control voltage an additional current that is added to the bias current.

2. The method according to claim 1 , wherein said control voltage is present between a gate terminal and a source terminal, respectively, of an additional transistor, the additional transistor generating said additional current on said node receiving the bias current.

3. The method according to claim 2 , further comprising decreasing said control voltage so as to slow said generation of the additional current until it stops, wherein the decrease in the control voltage is caused by the additional current generated by the additional transistor.

4. A method for generating a bias current for biasing a differential pair of transistors which include a first input, a second input, a first intermediate output, and a second intermediate output, the method comprising:
generating a bias current for biasing the first intermediate output and the second intermediate output;
generating a control voltage arising from a difference in potentials between the first input and the second input by amplifying a difference signal resulting from a difference between the potential on the first input and the potential on the second input; and
generating in response to the control voltage an additional current that is added to the bias current;
wherein generating the control voltage comprises:
generating a first control voltage arising from a positive difference in potentials between the first input and the second input, and
generating a second control voltage arising from a negative difference in potentials between the first input and the second input, and

wherein generating the additional current comprises:
generating in response to the first control voltage a first additional current being added to the bias current, and
generating in response to the second control voltage a second additional current that is added to the bias current.

5. An integrated circuit, comprising:
a differential pair of transistors including a first input, a second input, a first intermediate output, a second intermediate output;
a bias current generator configured to generate a bias current for biasing the first intermediate output and the second intermediate output; and
a control loop configured to generate a control voltage arising from a difference in potentials between a potential on the first input and a potential on a node that is configured to receive the bias current, and to generate in response to the control voltage an additional current that is added to the bias current for biasing the first intermediate output and the second intermediate output.

6. The integrated circuit according to claim 5 , wherein said control loop comprises an additional transistor configured to generate said additional current on said node, and is configured to generate said control voltage between a gate terminal and a source terminal, respectively, of the additional transistor.

7. The integrated circuit according to claim 6 , wherein said control loop responds to the additional current generated by the additional transistor by causing a decrease in said control voltage for slowing said generation of the additional current.

8. An integrated circuit, comprising:
a differential pair of transistors including a first input, a second input, a first intermediate output, a second intermediate output;
a bias current generator configured to generate a bias current for biasing the first intermediate output and the second intermediate output;
a control loop configured to generate a control voltage arising from a difference in potentials between the first input and the second input, and to generate in response to the control voltage an additional current that is added to the bias current for biasing the first intermediate output and the second intermediate output;
wherein the control loop comprises an amplifier configured to determine a difference between a potential on the first input and a potential on the second input, and to amplify a signal resulting from the difference so as to generate said control voltage; and
wherein said control loop is configured to generate, as said control voltage, a first control voltage arising from a positive difference in potentials between the first input and the second input and a second control voltage arising from a negative difference in potentials between the first input and the second input, and to generate, as said additional current, a first additional current that is added to the bias current, which generation is controlled by the first control voltage, and a second additional current that is added to the bias current, which generation is controlled by the second control voltage.

9. The integrated circuit according claim 8 , wherein said differential pair of transistors are input transistors for an operational amplifier.

10. An integrated circuit, comprising:
a first differential pair of transistors including a first input, a second input, and a first common source bias node;
a second differential pair of transistors including a third input, a fourth input, and a second common source bias node;
a first current source configured to source a first bias current to the common source bias node;
a transistor configured to generate a second bias current for application to the common source bias node;
an amplifier circuit having a first input configured to receive a voltage at the first input and a second input configured to receive a voltage at the second input, the amplifier circuit configured to determine a difference between the voltage at the first and second inputs and output a control voltage for application to a control terminal of said transistor; and
a switched circuit configured to selectively apply the first and second bias currents to the second common source bias node in response to a control signal.

11. The integrated circuit of claim 10 , wherein the first and third inputs are connected together and wherein the second and fourth inputs are connected together.

12. The integrated circuit of claim 10 , wherein the first differential pair of transistors further include first differential outputs, further comprising an output amplifier stage having inputs coupled to the first differential outputs.

13. The integrated circuit of claim 12 , wherein a gain bandwidth product of the amplifier circuit is substantially greater than a gain bandwidth product of the combined first differential pair of transistors and output amplifier.

14. The integrated circuit of claim 12 , further comprising an additional transistor configured to generate a third bias current for application to bias the output amplifier, and wherein the control voltage is further applied to a control terminal of said additional transistor.

15. An integrated circuit, comprising:
a first differential pair of transistors including a first input, a second input, and a first common source bias node;
a first current source configured to source a first bias current to the common source bias node;
a first transistor configured to generate a second bias current for ap

Assignees

• St Microelectronics Rousset

Inventors

• Binet Vincent
• Joly Yohan

Classifications

• H03F2203/45112

  the biasing of the differential amplifier being controlled from the input or the output signal · CPC title

• H03F3/45475 Primary

  using IC blocks as the active amplifying circuit · CPC title

• H03F3/45264 Primary

  Complementary cross coupled types · CPC title

• H03F2203/45236

  Two dif amps realised in MOS or JFET technology, one of them being of the p-channel type and the other one of the n-channel type, are coupled in parallel with their gates · CPC title

• H03F2203/45134

  the whole differential amplifier together with other coupled stages being fully differential realised · CPC title