Antenna with graded dielectirc and method of making the same

Patent metadata

Field	Value
Publication number	US-11031699-B2
Application number	US-201815892632-A
Country	US
Kind code	B2
Filing date	Feb 9, 2018
Priority date	Feb 9, 2018
Publication date	Jun 8, 2021
Grant date	Jun 8, 2021

Abstract

Some embodiments include packages and methods of making the packages. One of the packages includes a ground layer (e.g., a ground plane) of metal formed over a chip of die, an antenna element of metal formed over the ground layer, and a dielectric lens formed over the antenna element. The dielectric lens includes a plurality of dielectric layers that have graded dielectric constants in a decreasing order along a direction from the antenna element toward a top surface of the package.

First claim

The invention claimed is:

1. A package comprising:
a ground layer of metal over a chip of die;
an antenna over the ground layer; and
a dielectric lens over the antenna, the dielectric lens comprising a plurality of dielectric layers having graded dielectric constants along a direction from the antenna toward a top surface of the package, wherein horizontal dimensions of the plurality of dielectric layers of the dielectric lens increase along a direction from the antenna towards the top surface of the package such that the dielectric lens is in a taper shape with a top side broader than a bottom side.

2. The package of claim 1 , wherein the antenna is separated from the ground layer by a stack of dielectric spacers.

3. The package of claim 2 , wherein the stack of dielectric spacers comprise a same dielectric constant.

4. The package of claim 1 , wherein a horizontal dimension of the ground layer of metal is greater than a horizontal dimension of the antenna.

5. The package of claim 1 , wherein the dielectric constants of the plurality of dielectric layers of the dielectric lens are graded in a decreasing order along the direction from the antenna towards the top surface of the package.

6. The package of claim 1 , wherein the chip comprises silicon.

7. A method of making a package, comprising: forming a stack of dielectric spacers over a die; forming a ground layer of metal in a lower portion of the stack of dielectric spacers; forming an antenna in an upper portion of the stack of dielectric spacers, the antenna separated from the ground layer by a portion of the stack of dielectric spacers; and forming a dielectric lens over the antenna, the dielectric lens comprising a plurality of dielectric layers having graded dielectric constants in a decreasing order along a direction from the antenna toward a top surface of the package wherein the dielectric lens is formed to have widths of the plurality of dielectric layers increasing along the direction from the antenna towards the top surface of the package such that the dielectric lens is in a taper shape with a top side broader than a bottom side.

8. The method of claim 7 , wherein the ground layer is formed in a first redistribution layer in the lower portion of the stack of dielectric spacers, and wherein the antenna is formed in a second redistribution layer in the upper portion of the stack of dielectric spacers.

9. The method of claim 7 , further comprising forming a through slot in the ground layer to allow a power line to pass through the ground layer to electrically connect the chip and the antenna.

10. The method of claim 7 , further comprising forming opening into a printed circuit board over the top surface of the package to expose a top surface of the dielectric lens.

11. The method of claim 7 , further comprising forming through mold vias and solder bumps to solder a printed circuit board to the package.

12. The method of claim 11 , wherein forming through mold vias and solder bumps comprises:
forming a first through mold via and a first solder bump to electrically connect the printed circuit board and a first redistribution layer in the lower portion of the stack of dielectric spacers; and
forming a second through mold via and a second solder bump to electrically connect the printed circuit board and a second redistribution layer in the upper portion of the stack of dielectric spacers.

Assignees

• Intel Ip Corp

Inventors

• Maruthamuthu Saravana
• Waidhas Bernd
• Augustin Andreas
• Seidemann Georg

Classifications

• H10P14/412

  Deposition of metallic or metal-silicide materials · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/07236

  Soldering or alloying · CPC title

• H10W72/942

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title