Silicon carbide superjunction power semiconductor device and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-11031473-B2
Application number	US-201916558935-A
Country	US
Kind code	B2
Filing date	Sep 3, 2019
Priority date	Mar 3, 2017
Publication date	Jun 8, 2021
Grant date	Jun 8, 2021

Abstract

A power semiconductor device includes a semiconductor wafer having a first main side surface and a second main side surface. The semiconductor wafer includes a first semiconductor layer having a first conductivity type and a plurality of columnar or plate-shaped first semiconductor regions extending in the first semiconductor layer between the first main side surface and the second main side surface in a vertical direction perpendicular to the first main side surface and the second main side surface. The first semiconductor regions have a second conductivity type, which is different from the first conductivity type. Therein, the first semiconductor is a layer of hexagonal silicon carbide. The first semiconductor regions are regions of 3C polytype silicon carbide.

First claim

The invention claimed is:

1. A superjunction power semiconductor device comprising:
a semiconductor wafer having a first main side surface and a second main side surface, the semiconductor wafer including:
a first semiconductor layer having a first conductivity type;
a plurality of columnar or plate-shaped first semiconductor regions extending in the first semiconductor layer between the first main side surface and the second main side surface in a vertical direction perpendicular to the first main side surface and the second main side surface, the first semiconductor regions having a second conductivity type, which is different from the first conductivity type, wherein the first semiconductor layer is a layer of hexagonal silicon carbide, and wherein the first semiconductor regions are regions of 3C polytype cubic silicon carbide; and
a second semiconductor region of hexagonal silicon carbide separating the first semiconductor layer from the first semiconductor regions, wherein the second semiconductor region is of the second conductivity type.

2. The superjunction power semiconductor device according to claim 1 , wherein the first semiconductor layer is a drift layer having a thickness in a vertical direction of at least 3 μm and having a doping concentration below 2-10 17 cm −3 .

3. The superjunction power semiconductor device according to claim 2 , wherein the 3C polytype cubic silicon carbide is polycrystalline.

4. The superjunction power semiconductor device according to claim 1 , wherein the 3C polytype cubic silicon carbide is polycrystalline.

5. The superjunction power semiconductor device according to claim 4 , wherein the first semiconductor layer is single crystalline.

6. The superjunction power semiconductor device according to claim 1 , wherein the first semiconductor layer is a single crystalline.

7. The superjunction power semiconductor device according to claim 1 , wherein the hexagonal silicon carbide is 4H—SiC or 6H—SiC.

8. The superjunction power semiconductor device according to claim 1 , the semiconductor wafer comprising a second semiconductor layer on the first semiconductor layer and an electrode layer formed on the second semiconductor layer on a side opposite to the first semiconductor layer to form an ohmic contact to the second semiconductor layer, wherein the second semiconductor layer has a doping concentration which is at least 10 times as high as the doping concentration in the first semiconductor layer.

9. The superjunction power semiconductor device according to claim 1 , wherein each pair of first semiconductor regions neighboring to each other in a horizontal direction parallel to the first main side surface and the second main side surface are separated from each other in the horizontal direction by a portion of the first semiconductor layer so that the first semiconductor regions alternate with the portions of the first semiconductor layer in the horizontal direction.

10. The superjunction power semiconductor device according to claim 9 , wherein for each first semiconductor region a vertical of the first semiconductor region in a vertical direction perpendicular to the first main side surface and the second main side surface is at least two times a horizontal width of the first semiconductor region in the horizontal direction, wherein a vertical width of any first semiconductor region is a maximum width of that first semiconductor region in the vertical direction and wherein a horizontal width of any first semiconductor region is a maximum width of that first semiconductor region in the horizontal direction.

11. The superjunction power semiconductor device according to claim 10 , wherein a vertical width of each first semiconductor region is at least 3 μm.

12. The superjunction power semiconductor device according to claim 9 , wherein a distance between each pair of neighboring first semiconductor regions is in a range from 2 μm to 20 μm.

13. The superjunction power semiconductor device according to claim 10 , wherein a vertical width of each first semiconductor region is at least 4 μm.

14. The superjunction power semiconductor device according to claim 1 , wherein each first semiconductor region extends into the first semiconductor layer in the vertical direction to a depth of at least 3 μm, from a first main side of the first semiconductor layer facing the first main side surface of the semiconductor wafer.

15. A method for manufacturing a superjunction power semiconductor device, the method comprising:
including a semiconductor wafer having a first main side surface and a second main side surface;
forming a first semiconductor layer in the semiconductor wafer, the first semiconductor layer having a first conductivity type, wherein the first semiconductor layer is a layer of hexagonal silicon carbide;
forming a plurality of columnar or plate-shaped first semiconductor regions in the first semiconductor layer, wherein the plurality of columnar or plate-shaped first semiconductor regions extend between the first main side surface and the second main side surface in a vertical direction perpendicular to the first main side surface and the second main side surface, wherein the first semiconductor regions having a second conductivity type different from the first conductivity type, wherein the first semiconductor regions are separated from the first semiconductor layer by a second semiconductor region of hexagonal silicon carbide having the second conductivity type, and wherein the first semiconductor regions are regions of 3C polytype cubic silicon carbide;
forming the first semiconductor layer as a layer of hexagonal silicon carbide, wherein the first semiconductor layer has a first main side and a second main side opposite to the first main side;
forming a plurality of trenches in the first semiconductor layer from its first main side; and
refilling the trenches with a layer of cubic silicon carbide having second conductivity type different from the first conductivity type to form the first semiconductor regions as columnar or plate-shaped regions of 3C polytype cubic silicon carbide, which extend from the first main side into the first semiconductor layer.

16. The method according to claim 15 , the method further comprising a step of forming a power device cell at the first main side of the first semiconductor layer in an area between two of the first semiconductor regions neighboring to each other in a horizontal direction parallel to the first main side and the second main side.

17. The method according to claim 16 , wherein refilling the trenches with the layer of cubic silicon carbide is done by chemical vapor deposition at a temperature below 1100° C.

18. The method according to claim 15 , wherein refilling the trenches with the layer of 3C polytype cubic silicon is done by chemical vapor deposition at a temperature below 1100° C.

19. A superjunction power semiconductor device comprising:
a first semiconductor layer comprising hexagonal silicon carbide having a first conductivity type;
a first semiconductor region comprising 3C polytype cubic silicon carbide arranged in the first semiconductor region, the first semiconductor region having a second conductivity type different from the first conductivity type; and
a second semiconductor region comprising hexagonal silicon carbide surrounding the first semiconductor region, the second semiconductor region having the second conductivity type.

20. The superjunction power semiconductor device of claim 19 , further comprising:

Assignees

• Abb Power Grids Switzerland Ag

Inventors

• Bauer Friedhelm
• Knoll Lars
• Bellini Marco
• Minamisawa Renato
• Vemulapati Umamaheswara

Classifications

• H10D62/111

  Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures · CPC title

• H10D30/668

  having trench gate electrodes, e.g. UMOS transistors · CPC title

• H10D30/0297

  using recessing of the gate electrodes, e.g. to form trench gate electrodes · CPC title

• H10D8/60

  Schottky-barrier diodes · CPC title

• H10D8/00

  Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00) · CPC title