Silicon carbide stacked substrate and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-11031238-B2
Application number	US-201816484306-A
Country	US
Kind code	B2
Filing date	Jan 30, 2018
Priority date	Feb 20, 2017
Publication date	Jun 8, 2021
Grant date	Jun 8, 2021

Abstract

In a silicon carbide stacked substrate, the efficiency of converting the basal plane dislocation (BPD) which is a fault to deteriorate the current-carrying reliability into a threading edge dislocation (TED) which is a harmless fault is improved, thereby improving the reliability of the silicon carbide stacked substrate. As means therefor, in a silicon carbide stacked substrate including a SiC substrate and a buffer layer and a drift layer which are epitaxial layers sequentially formed on the SiC substrate, a semiconductor layer having an impurity concentration lower than those of the SiC substrate and the buffer layer and higher than that of the drift layer is formed between the SiC substrate and the buffer layer so as to be in contact with an upper surface of the SiC substrate.

First claim

The invention claimed is:

1. A silicon carbide stacked substrate comprising:
a first substrate of a first conductivity type which is a hexagonal semiconductor substrate containing silicon carbide;
a first semiconductor layer of the first conductivity type formed on the first substrate and containing silicon carbide;
a second semiconductor layer of the first conductivity type formed on the first semiconductor layer and containing silicon carbide; and
a third semiconductor layer of the first conductivity type formed on the second semiconductor layer and containing silicon carbide,
wherein the first semiconductor layer is in contact with an upper surface of the first substrate,
wherein a first impurity concentration of the first semiconductor layer is lower than any of a second impurity concentration of the second semiconductor layer and a fourth impurity concentration of the upper surface of the first substrate and is higher than a third impurity concentration of the third semiconductor layer, and the second impurity concentration is higher than the third impurity concentration,
wherein the first impurity concentration is 1×10 17 cm −3 or lower, and
wherein the fourth impurity concentration is higher than 1×10 18 cm −3 .

2. The silicon carbide stacked substrate according to claim 1 ,
wherein the first impurity concentration is higher than 1×10 16 cm −3 and 1×10 17 cm −3 or lower.

3. The silicon carbide stacked substrate according to claim 2 ,
wherein the fourth impurity concentration and the second impurity concentration are 1×10 17 cm −3 or higher.

4. The silicon carbide stacked substrate according to claim 1 ,
wherein the fourth impurity concentration is higher than the second impurity concentration.

5. The silicon carbide stacked substrate according to claim 1 ,
wherein the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are epitaxial layers.

6. A silicon carbide stacked substrate comprising:
a second substrate of a first conductivity type which is a hexagonal semiconductor substrate containing silicon carbide;
a fifth semiconductor layer of the first conductivity type formed on the second substrate and containing silicon carbide;
a first semiconductor layer of the first conductivity type formed on the fifth semiconductor layer and containing silicon carbide;
a second semiconductor layer of the first conductivity type formed on the first semiconductor layer and containing silicon carbide; and
a third semiconductor layer of the first conductivity type formed on the second semiconductor layer and containing silicon carbide,
wherein the first semiconductor layer is in contact with an upper surface of the fifth semiconductor layer,
wherein a first impurity concentration of the first semiconductor layer is lower than any of a second impurity concentration of the second semiconductor layer and a fifth impurity concentration of the upper surface of the fifth semiconductor layer and is higher than a third impurity concentration of the third semiconductor layer, the second impurity concentration is higher than the third impurity concentration, and a sixth impurity concentration of the second substrate is lower than the second impurity concentration,
wherein an upper surface of the third semiconductor layer constitutes an outermost surface of the silicon carbide stacked substrate,
wherein the fifth impurity concentration is 1×10 17 cm −3 or higher,
wherein the sixth impurity concentration is lower than 1×10 17 cm −3 , and
wherein of the plurality of layers provided between the second substrate and the third semiconductor layer, only the first semiconductor layer has an impurity concentration of 1×10 17 cm −3 or lower.

7. The silicon carbide stacked substrate according to claim 6 ,
wherein the first impurity concentration is higher than 1×10 16 cm −3 and 1×10 17 cm −3 or lower.

8. The silicon carbide stacked substrate according to claim 7 ,
wherein the fifth impurity concentration and the second impurity concentration are 1×10 17 cm −3 or higher.

9. The silicon carbide stacked substrate according to claim 6 ,
wherein the fifth semiconductor layer, the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are epitaxial layers.

10. The silicon carbide stacked substrate according to claim 6 , further comprising:
a seventh semiconductor layer of the first conductivity type formed on the first semiconductor layer and containing silicon carbide; and
an eighth semiconductor layer of the first conductivity type formed on the seventh semiconductor layer and containing silicon carbide,
wherein the second semiconductor layer is formed on the eighth semiconductor layer,
the eighth semiconductor layer is in contact with an upper surface of the seventh semiconductor layer, and
an eighth impurity concentration of the eighth semiconductor layer is lower than any of the second impurity concentration and a seventh impurity concentration of the upper surface of the seventh semiconductor layer and is higher than the third impurity concentration.

11. The silicon carbide stacked substrate according to claim 6 ,
wherein a lower surface of the fifth semiconductor layer has a ninth impurity concentration lower than the fifth impurity concentration, and
the fifth semiconductor layer has a concentration gradient in which an impurity concentration gradually increases from the lower surface of the fifth semiconductor layer toward the upper surface of the fifth semiconductor layer.

12. The silicon carbide stacked substrate according to claim 1 ,
wherein a relationship of the first, second, third, and fourth impurity concentrations of said first, second, third, and fourth semiconductor layers, respectively, is the fourth impurity concentration>the second impurity concentration>the first impurity concentration>the third impurity concentration.

13. The silicon carbide stacked substrate according to claim 1 ,
wherein a film thickness of the second semiconductor layer is 0.5 to 8 μm.

Assignees

• Hitachi Metals Ltd

Inventors

• Konishi Kumiko
• Oouchi Kiyoshi
• Kobayashi Keisuke
• Shima Akio

Classifications

• H10P14/3442

  N-type · CPC title

• H10P14/3408

  Silicon carbide · CPC title

• H10P14/3251

  consisting of three or more layers · CPC title

• H10P14/3248

  consisting of two layers · CPC title

• H10P14/3208

  Silicon carbide · CPC title