Continuously variable precision and linear floating resistor using metal-oxide-semiconductor field-effect transistors

Patent metadata

Field	Value
Publication number	US-11031158-B2
Application number	US-201816757648-A
Country	US
Kind code	B2
Filing date	Nov 16, 2018
Priority date	Aug 13, 2018
Publication date	Jun 8, 2021
Grant date	Jun 8, 2021

Abstract

A circuit for realizing a precision and linear floating resistor, using MOSFET devices, is disclosed. A linear floating voltage-controlled resistor (LFVCR) is realized using a MOSFET with a gate drive means and a substrate drive means to provide a feedback of the common-mode voltage across the source-drain terminals to the gate and substrate terminals. Two such LFVCR circuits using matched MOSFET devices having independent substrates, along with an op-amp based negative feedback loop, are used to realize a continuously variable precision and linear floating resistor, whose value can be controlled by a combination of variable voltage, current, and resistor. Further embodiments are disclosed for realizing a resistor mirror circuit with multiple floating resistors, improving the linearity by using LFVCR circuits with complementary MOSFET devices, realizing a resistor with scaled-up resistance and extended voltage range, and realizing a resistor with scaled-down resistance and extended current range.

First claim

We claim:

1. A circuit for realizing a continuously variable precision and linear floating resistor, comprising:
(i) at least two linear floating voltage-controlled resistor (LFVCR) circuits comprising a first LFVCR circuit and a second LFVCR circuit, wherein each LFVCR circuit comprises (a) two resistor terminals, a control terminal, and a bias terminal; (b) a MOSFET having two interchangeable source-drain terminals, a gate terminal, and a substrate terminal; (c) a gate drive means having three inputs, with interchangeable source-drain terminals of the MOSFET connected as the two inputs and the control terminal connected as the third input, and an output connected to the gate terminal of the MOSFET; and (d) a substrate drive means having three inputs, with the interchangeable source-drain terminals of the MOSFET connected as the two inputs and the bias terminal connected as the third input, and an output connected to the substrate terminal of the MOSFET;
(ii) a bias voltage means with an output terminal connected to the bias terminal of each LFVCR circuit for providing a bias voltage (V BB );
(iii) an op amp having noninverting and inverting input terminals, and an output terminal connected to the control terminal of each LFVCR circuit for providing a control voltage (v C ); and
(iv) three voltage sources comprising a first voltage source, a second voltage source, and a third voltage source, and a resistor;
wherein the MOSFET devices of the LFVCR circuits are matched and have independent substrate terminals, the first voltage source is connected to the first resistor terminal of the first LFVCR circuit, the second voltage source is connected in series with the resistor to the second resistor terminal of the first LFVCR circuit and to the inverting input terminal of the op amp, the third voltage source is connected to the noninverting input terminal of the op amp, and the resistor terminals of the second LFVCR circuit serve as the resistor terminals of the circuit.

2. The circuit as claimed in claim 1 , wherein the gate drive means and the substrate drive means are adder circuits receiving three inputs and generating an output by adding the average of the first input and the second input to the third input.

3. The circuit as claimed in claim 1 , wherein the first LFVCR circuit and the op amp form a negative feedback loop to compensate the resistance of the circuit against the device parameter variations, thereby resulting in a precision resistor.

4. The circuit as claimed in claim 1 , wherein the resistance across the resistor terminals of the second LFVCR circuit tracks the resistance across the resistor terminals of the first LFVCR circuit.

5. The circuit as claimed in claim 1 , wherein the resistance across the resistor terminals of the circuit is continuously variable using a combination of three voltage sources and a resistor.

6. The circuit as claimed in claim 1 , wherein the resistance across the resistor terminals is directly proportional to the difference of the voltages of the first voltage source and the third voltage source; inversely proportional to the difference of the voltages of the third voltage source and the second voltage source, and directly proportional to the resistance of the resistor.

7. The circuit as claimed in claim 1 , wherein the third voltage source can be set as zero by connecting the noninverting input of the op amp to the ground terminal.

8. The circuit as claimed in claim 1 , wherein the circuit is realized as part of an integrated circuit using a CMOS process permitting MOSFET devices having independent substrates.

9. The circuit as claimed in claim 1 , wherein the gate drive means of each LFVCR circuit comprises at least one op amp and at least five resistors interconnected as an adder circuit to generate an output by adding the average of the first input and the second input to the third input.

10. The circuit as claimed in claim 1 , wherein the substrate drive means of each LFVCR circuit comprises at least one op amp and at least five resistors interconnected as an adder circuit to generate an output by adding the average of the first input and the second input to the third input.

11. The circuit as claimed in claim 1 , wherein the bias voltage means comprises an op amp and at least two resistors to generate a buffered dc voltage as the bias voltage (V BB ).

12. The circuit as claimed in claim 1 , wherein the resistance across the resistor terminals of the circuit is controlled by the first voltage source and the third voltage source, and optionally by a current source connected to the second resistor terminal of the first LFVCR circuit.

13. The circuit as claimed in claim 1 , wherein the MOSFET devices are n-channel devices.

14. The circuit as claimed in claim 1 , wherein the MOSFET devices are p-channel devices.

15. The circuit as claimed in claim 1 further comprising a third LFVCR circuit, wherein the bias terminal and the control terminal of the third LFVCR circuit are connected to the corresponding terminals of the second LFVCR circuit and the resistance across the terminals of the third LFVCR circuit tracks the resistance across the terminals of the second LFVCR circuit, thereby realizing a resistor mirror with independent resistor terminals.

16. A circuit for realizing a continuously variable precision and linear floating resistor, comprising:
(i) a first pair of linear floating voltage-controlled resistor (LFVCR) circuits comprising a first LFVCR circuit and a second LFVCR circuit, and a second pair of LFVCR circuits comprising a third LFVCR circuit and a fourth LFVCR circuit, wherein each LFVCR circuit comprises (a) two resistor terminals, a control terminal, a bias terminal; (b) a MOSFET; (c) a gate drive means having three inputs, with the interchangeable source-drain terminals of the MOSFET connected as the two inputs and the control terminal connected as the third input, and an output connected to the gate terminal of the MOSFET; and (d) a substrate drive means having three inputs, with the interchangeable source-drain terminals of the MOSFET connected as the two inputs and the bias terminal connected as the third input, and an output connected to the substrate terminal of the MOSFET;
(ii) at least two bias voltage means comprising a first bias voltage means with an output terminal connected to the bias terminals of the first pair of LFVCR circuits for providing a first bias voltage (V BB1 ), and a second bias voltage means with an output terminal connected to the bias terminals of the second pair of LFVCR circuits for providing a second bias voltage (V BB2 );
(iii) at least two op amps comprising a first op amp having noninverting and inverting input terminals and an output terminal connected to the control terminals of the first pair of LFVCR circuits for providing a first control voltage (v CN ) and a second op amp having noninverting and inverting input terminals and an output terminal connected to the control terminals of the second pair of LFVCR circuits for providing a second control voltage (v CP );
(iv) at least two voltage sources comprising a first voltage source and a second voltage source, two resistors comprising a first resistor and a second resistor, and at least two inverting unity gain amplifiers comprising a first inverting unity gain amplifier and a second inverting unity gain amplifier;
wherein a combination of the first pair of LFVCR circuits with n-channel matched MOSFET devices having independent substrate terminals and the second pair of LFVCR circuits with p-channel matched MOSFET devices having independent substrate terminals a

Assignees

• Indian Inst Technology Bombay

Inventors

• Pandey Prem Chand
• Debbarma Shibam
• Marla Vikas
• Tiwari Nitya
• Holani Rani
• Sharma Dinesh Kumar

Classifications

• H03K17/687

  the devices being field-effect transistors · CPC title

• H01C7/10 Primary

  voltage responsive, i.e. varistors · CPC title

• H03H11/53 Primary

  simulating resistances; simulating resistance multipliers · CPC title

• H03H11/54

  Modifications of networks to reduce influence of variations of temperature · CPC title