Apparatus having memory arrays and having trim registers associated with memory array access operation commands

Patent metadata

Field	Value
Publication number	US-11031081-B2
Application number	US-201916654308-A
Country	US
Kind code	B2
Filing date	Oct 16, 2019
Priority date	Dec 21, 2012
Publication date	Jun 8, 2021
Grant date	Jun 8, 2021

Abstract

Memories include a controller that, in response to receiving a command to perform an access operation on an array of memory cells, might be configured to perform the access operation on the array of memory cells using trims corresponding to trim settings for the access operation. The controller, in response to receiving a command or a command sequence while performing the access operation that is indicative of a desire to suspend the access operation and load updated trim settings, might be further configured to suspend the access operation, load updated trim settings for the access operation into a particular trim register of a plurality of trim registers, set updated trims for the access operation in response to the updated trim settings in the particular trim register, and resume the access operation using the updated trims.

First claim

What is claimed is:

1. A memory, comprising:
an array of memory cells;
a plurality of trim registers; and
a controller for access of the array of memory cells;
wherein the controller is configured to:
in response to receiving a command to perform an access operation on the array of memory cells, perform the access operation on the array of memory cells using trims corresponding to trim settings for the access operation; and
in response to receiving a command or a command sequence while performing the access operation that is indicative of a desire to suspend the access operation and load updated trim settings:
suspend the access operation;
load updated trim settings for the access operation into a particular trim register of the plurality of trim registers;
set updated trims for the access operation in response to the updated trim settings in the particular trim register; and
resume the access operation using the updated trims.

2. The memory of claim 1 , wherein the command sequence indicative of a desire to suspend the access operation and load updated trim settings comprises an initial command to suspend the access operation and a subsequent command to load the updated trim settings.

3. The memory of claim 2 , wherein the subsequent command to load the updated trim settings is associated with the updated trim settings to be received by the memory.

4. The memory of claim 2 , wherein the controller, in response to receiving the initial command to suspend the access operation, is further configured to store the trim settings to the particular trim register prior to loading the updated trim settings into the particular trim register.

5. The memory of claim 1 , wherein the controller being configured to perform the access operation on the array of memory cells using trims corresponding to the trim settings for the access operation comprises the controller further being configured to set the trims in response to the trim settings prior to performing the access operation.

6. The memory of claim 5 , wherein the controller is further configured to load a trim register of the plurality of trim registers with the trim settings prior to setting the trims.

7. The memory of claim 6 , wherein the controller is further configured to load the trim register of the plurality of trim registers with the trim settings in response to receiving the command to perform the access operation.

8. The memory of claim 1 , wherein the controller being configured to resume the suspended access operation comprises the controller being configured to resume the suspended access operation in response to receiving a command to resume the suspended access operation.

9. The memory of claim 1 , wherein the controller being configured to resume the suspended access operation comprises the controller being configured to resume the suspended access operation in response to completion of a different operation initiated after receiving the command or command sequence indicative of a desire to suspend the access operation and load updated trim settings.

10. A memory, comprising:
an array of memory cells;
a plurality of trim registers; and
a controller for access of the array of memory cells;
wherein the controller is configured to:
in response to receiving a command to perform an access operation on a grouping of memory cells of the array of memory cells:
set trims in response to trim settings corresponding to the command to perform the access operation; and
perform the access operation on the grouping of memory cells using the trims; and

in response to receiving a command to suspend the access operation while performing the access operation and receiving a command to load updated trim settings subsequent to receiving the command to suspend the access operation:
suspend the access operation;
load updated trim settings into a particular trim register of the plurality of trim registers;
set updated trims for the access operation in response to the updated trim settings of the particular trim register; and
resume the access operation using the updated trims in response to a criteria selected from a group consisting of receiving a command to resume the suspended access operation, and completion of an intervening operation performed while the access operation is suspended.

11. The memory of claim 10 , wherein the controller, in response to receiving the command to suspend the access operation, is further configured to store the trim settings to the particular trim register prior to loading the updated trim settings into the particular trim register.

12. The memory of claim 11 , wherein the controller is further configured to load the updated trim settings into the particular trim register in response to the receiving the command to load the updated trim settings.

13. The memory of claim 10 , wherein the controller, in response to receiving a subsequent command to perform the intervening operation on a different grouping of memory cells of the array of memory cells while the access operation is suspended, is further configured to perform the intervening operation on the different grouping of memory cells.

14. The memory of claim 10 , wherein the controller is further configured to load a trim register of the plurality of trim registers associated with the command to perform the access operation with the trim settings while the memory is performing a prior access operation on a different grouping of memory cells of the array of memory cells.

15. The memory of claim 10 , wherein the controller being configured to set the trims in response to the trim settings comprises the controller being configured to set parameters to be utilized by the memory to perform the access operation on the grouping of memory cells in response to the trim settings.

16. The memory of claim 15 , wherein the controller being configured to set the parameters to be utilized by the memory to perform the access operation comprises the controller being configured to set at least one parameter selected from a group consisting of voltages to be applied during the access operation, voltage differentials to be utilized during the access operation, and quantities to be utilized during the access operation.

17. The memory of claim 10 , wherein the controller being configured to set the updated trims for the access operation is further in response to the selected criteria for resuming the access operation.

18. A memory, comprising:
an array of memory cells;
a plurality of trim registers; and
a controller for access of the array of memory cells;
wherein the controller is configured to:
in response to receiving a command to perform an access operation on a grouping of memory cells of the array of memory cells:
set trims in response to trim settings corresponding to the command to perform the access operation; and
perform the access operation on the grouping of memory cells using the trims;

in response to receiving a command to suspend the access operation while performing the access operation, wherein the command to suspend the access operation is further indicative of a desire to load updated trim settings for the access operation:
load the updated trim settings into a particular trim register of the plurality of trim registers; and
set updated trims for the access operation in response to the updated trim settings of the particular trim register; and

in response to receiving a command to resume the suspended access operation:
resume the suspended access operation using the updated trims.

Assignees

• Micron Technology Inc

Inventors

• Grunzke Terry

Classifications

• G11C16/06

  Auxiliary circuits, e.g. for writing into memory · CPC title

• G11C7/1072

  for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories · CPC title

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G06F2212/7207

  management of metadata or control data · CPC title