Soft bit read mode selection for non-volatile memory

Patent metadata

Field	Value
Publication number	US-11029889-B1
Application number	US-201916723192-A
Country	US
Kind code	B1
Filing date	Dec 20, 2019
Priority date	Dec 20, 2019
Publication date	Jun 8, 2021
Grant date	Jun 8, 2021

Abstract

Apparatuses, systems, and methods are presented for reading data. A controller may be configured to select a read mode from a plurality of read modes for reading data from a region of a non-volatile memory array. The plurality of read modes may include at least a time-based soft bit read mode. The controller may be configured to apply a set of bias conditions to cells of a region so that bit line currents associated with the cells of the region affect voltages at capacitors associated with the cells of the region. The controller may be configured to, in response to selecting a time-based soft bit read mode, read hard bits and soft bits for a region by sensing capacitor voltages resulting from an applied set of bias conditions, at multiple integration times.

First claim

What is claimed is:

1. An apparatus, comprising:
an array of non-volatile memory cells; and
a controller configured to:
select a read mode from a plurality of read modes for reading data from a region of the array, the plurality of read modes comprising at least a time-based soft bit read mode;
apply a set of bias conditions to cells of the region such that bit line currents associated with the cells of the region affect voltages at capacitors associated with the cells of the region; and
in response to selecting the time-based soft bit read mode, read hard bits and soft bits for the region by sensing the capacitor voltages resulting from the applied set of bias conditions, at multiple integration times.

2. The apparatus of claim 1 , wherein:
the plurality of read modes further comprises a hard bit read mode and a bias-based soft bit read mode; and
the controller is further configured to:
in response to selecting the hard bit read mode, read hard bits for the region by sensing the capacitor voltages resulting from the applied set of bias conditions, at a single integration time; and
in response to selecting the bias-based soft bit read mode, read hard bits and soft bits for the region by sensing the capacitor voltages resulting from the applied set of bias conditions, applying one or more additional sets of bias conditions, and sensing the capacitor voltages resulting from the one or more additional sets of bias conditions.

3. The apparatus of claim 1 , wherein the time-based soft bit read mode is a default read mode for the controller.

4. The apparatus of claim 1 , wherein the controller is configured to sense capacitor voltages at two integration times in the time-based soft bit read mode, and to sense capacitor voltages at three integration times in a second time-based soft bit read mode.

5. The apparatus of claim 1 , wherein the controller is configured to select the read mode based on information included in a read command received by the controller.

6. The apparatus of claim 1 , wherein the multiple integration times comprise a set of times selected by the controller based on information included in a read command received by the controller.

7. The apparatus of claim 1 , wherein the controller is configured to select the read mode based on metadata recorded at write time for the region.

8. The apparatus of claim 1 , wherein the controller is configured to select the read mode based on a comparison of the current time and temperature to time and temperature metadata recorded at write time for the region.

9. The apparatus of claim 1 , wherein the controller is configured to select the read mode based on error correction information for the region.

10. The apparatus of claim 1 , wherein the controller is configured to select the read mode based on error correction information for a second region of the array, and on metadata recorded at write time for the region and the second region.

11. The apparatus of claim 1 , wherein the multiple integration times comprise a set of times selected by the controller based on one or more of: metadata for the region, error correction information for the region, error correction information for a second region of the array, and metadata recorded at write time for the second region.

12. A method, comprising:
determining whether to use a time-based soft bit read mode for reading data from a region of non-volatile memory;
applying a set of bias voltages to cells of the region such that states of the cells affect analog voltages at sense amplifiers associated with the cells; and
in response to determining to use the time-based soft bit read mode, reading hard bits and soft bits for the region by converting the analog voltages affected by the applied bias voltages to digital sense amplifier results, at multiple integration times.

13. The method of claim 12 , further comprising selecting whether to convert the analog voltages to digital sense amplifier results at two integration times or at three integration times.

14. The method of claim 12 , further comprising determining the multiple integration times based on one or more of: metadata for the region, error correction information for the region, error correction information for a second region of the non-volatile memory, and metadata recorded at write time for the second region.

15. The method of claim 12 , wherein determining whether to use a time-based soft bit read mode comprises comparing a current time and temperature to time and temperature metadata recorded at write time for the region.

16. The method of claim 12 , wherein determining whether to use a time-based soft bit read mode is based on error correction information for the region.

17. The method of claim 12 , wherein determining whether to use a time-based soft bit read mode is based on error correction information for a second region of the non-volatile memory, and on metadata recorded at write time for the region and the second region.

18. An apparatus, comprising:
means for selecting a read mode from a plurality of read modes for reading data from a region of non-volatile memory, the plurality of read modes comprising at least a time-based soft bit read mode;
means for producing analog voltages based on data stored by cells of the region; and
means for digitizing the analog voltages at a number of integration times based on the selected read mode.

19. The apparatus of claim 18 , wherein the means for selecting a read mode comprises comprising means for comparing a current time and temperature to time and temperature metadata recorded at write time for the region.

20. The apparatus of claim 18 , further comprising means for determining the integration times based on one or more of: metadata for the region, error correction information for the region, error correction information for a second region of the non-volatile memory, and metadata recorded at write time for the second region.

Assignees

• Western Digital Tech Inc

Inventors

• Sharon Eran
• Bazarsky Alex
• Alrod Idan

Classifications

• G06F11/1012

  using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence) · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C13/004 Primary

  Reading or sensing circuits or methods · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0659 Primary

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title