Electronic apparatus and control method for adjusting priority of an application based on activations

US11029747B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11029747-B2
Application numberUS-201916368255-A
CountryUS
Kind codeB2
Filing dateMar 28, 2019
Priority dateMar 30, 2018
Publication dateJun 8, 2021
Grant dateJun 8, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

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The time required for transition from an on-state to a suspend state is reduced. An electronic apparatus includes: a memory and a memory; a current control unit that performs a control to shut off supply of current to the memory; and a memory management unit that allocates a memory region in either the memory or the memory based on preference information indicating a memory region that needs to be preferentially allocated in the memory. For example, the preference information includes association with a first priority as a degree at which a memory region to be used by an application needs to be preferentially allocated in the memory, and when receiving a request of allocation of the memory region from the application, the memory management unit more preferentially allocates the memory region in the memory as the first priority associated with the application in the preference information is higher.

First claim

Opening claim text (preview).

The invention claimed is: 1. An electronic apparatus comprising: a plurality of volatile memories that include a first memory and a second memory; a current control circuit that performs a control to shut off supply of current to the second memory; and a memory management circuit that allocates a memory region in either the first memory or the second memory based on a first threshold and preference information indicating a memory region that needs to be preferentially allocated in the first memory, wherein the preference information includes association between an application and a first priority, the application operating using the plurality of the volatile memories, the first priority being a degree at which a memory region to be used by the application needs to be preferentially allocated in the first memory, the memory management circuit acquires a frequency at which the application is activated, the memory management circuit calculates an adjusted first priority using the first priority associated with the application in the preference information and the frequency at which the application is activated, and calculates an adjusted first threshold using the first threshold and the frequency at which the application is activated, and when the memory management circuit receives a request of allocation of the memory region from the application, the memory management circuit allocates the memory region in the first memory if the adjusted first priority associated with the application in the preference information is higher than the adjusted first threshold. 2. The electronic apparatus according to claim 1 , wherein: the preference information includes association between a file and a second priority, the file being placed in the plurality of the volatile memories, the second priority being a degree at which a memory region in which the file is placed needs to be preferentially allocated in the first memory; and when the memory management circuit receives a request of allocation of the memory region in which the file needs to be placed, the memory management circuit more preferentially allocates the memory region in the first memory if the second priority associated with the file in the preference information is higher than a second threshold. 3. The electronic apparatus according to claim 1 , wherein the memory management circuit copies data stored in the second memory, to the first memory, before the current control circuit shuts off the supply of the current to the second memory. 4. The electronic apparatus according to claim 1 , wherein when the memory management circuit allocates the memory region across two or more non-volatile memories including the second memory of the plurality of the volatile memories, the memory management circuit copies data stored in a partial region, to the first memory, before the current control circuit shuts off the supply of the current to the second memory, the partial region being a region of the memory region allocated and being included in the second memory. 5. The electronic apparatus according to claim 1 , wherein: the current control circuit further performs a control to shut off supply of current to a controlled hardware device, the controlled hardware device being a previously determined hardware device of one or more hardware devices included in the electronic apparatus; and the memory management circuit further stores state information in the first memory, before the current control circuit shuts off the supply of the current to the controlled hardware device, the state information indicating a state of a driver that controls the controlled hardware device, and copies the state information to the driver, after the current control circuit restores the supply of the current to the controlled hardware device. 6. The electronic apparatus according to claim 5 , wherein the memory management circuit further stores completion information in the first memory, before the current control circuit shuts off the supply of the current to the controlled hardware device, the completion information indicating completion of the storing of the state information, and copies the state information to the driver when it is judged that the completion information is stored in the first memory, after the current control circuit restores the supply of the current to the controlled hardware device. 7. The electronic apparatus according to claim 5 , wherein: the memory management circuit further stores partial completion information in the first memory whenever the memory management circuit stores state information in the first memory, before the current control circuit shuts off the supply of the current to the controlled hardware device, the state information indicating states of one or more drivers of a plurality of the drivers, the partial completion information indicating completion of the storing of the state information; and the memory management circuit refers to the partial completion information stored in the first memory, (a) returns the state information to a driver that is of the plurality of the drivers and for which the state information is stored in the first memory, and (b) initializes a driver that is of the plurality of the drivers and for which the state information is not stored in the first memory, after the current control circuit restores the supply of the current to the controlled hardware device. 8. The electronic apparatus according to claim 1 , wherein: the electronic apparatus further comprises an operation circuit that receives an operation to cause the electronic apparatus to transition from an off-state to an on-state, from a user; the memory management circuit further estimates an estimated on time point, the estimated on time point being a time point when the electronic apparatus transitions from the off-state to the on-state after a present time point; and the current control circuit further performs the control to shut off the supply of the current to the second memory, when a time length from the present time point to the estimated on time point is longer than a predetermined length, and performs a control to restore the supply of the current to the second memory, when the time length from the present time point to the estimated on time point is shorter than a predetermined length. 9. A control method for an electronic apparatus including a plurality of volatile memories that include a first memory and a second memory, the control method comprising: performing a control to shut off supply of current to the second memory; and allocating a memory region in either the first memory or the second memory based on a first threshold and preference information indicating a memory region that needs to be preferentially allocated in the first memory, wherein the preference information includes association between an application and a first priority, the application operating using the plurality of the volatile memories, the first priority being a degree at which a memory region to be used by the application needs to be preferentially allocated in the first memory, acquiring a frequency at which the application is activated, calculating an adjusted first priority using the first priority associated with the application in the preference information and the frequency at which the application is activated, calculating an adjusted first threshold using the first threshold and the frequency at which the application is activated, and when receiving a request of allocation of the memory region from the application, allocating the memory region in the first memory if the adjusted first priority associated with the application in the preference information

Assignees

Inventors

Classifications

  • G06F1/3275Primary

    Power saving in memory, e.g. RAM, cache · CPC title

  • Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

  • of memory devices · CPC title

  • Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands · CPC title

  • by switching off individual functional units in the computer system · CPC title

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What does patent US11029747B2 cover?
The time required for transition from an on-state to a suspend state is reduced. An electronic apparatus includes: a memory and a memory; a current control unit that performs a control to shut off supply of current to the memory; and a memory management unit that allocates a memory region in either the memory or the memory based on preference information indicating a memory region that needs to…
Who is the assignee on this patent?
Panasonic Ip Man Co Ltd
What technology area does this patent fall under?
Primary CPC classification G06F1/3275. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jun 08 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).