Systems and methods for controlling instantaneous current changes in parallel processors

Patent metadata

Field	Value
Publication number	US-11029745-B2
Application number	US-201816184934-A
Country	US
Kind code	B2
Filing date	Nov 8, 2018
Priority date	Aug 31, 2018
Publication date	Jun 8, 2021
Grant date	Jun 8, 2021

Abstract

Systems and methods are disclosed method for controlling instantaneous current changes in parallel processors with arrays of parallel computing elements, such as neural processors. An exemplary method comprises monitoring the array of computing elements and determining a transition from a first activity level of the array to a second activity level of the array, such as an idle-to-active or active-to-idle transition. Once a transition is determined, the array is selectively controlled to minimize the instantaneous current change from the transition from the first activity level to the second activity level.

First claim

What is claimed is:

1. A method for controlling an instantaneous current change in a parallel processor, the method comprising:
monitoring an array of computing elements of the processor, the computing elements configured to operate independently of each other in parallel;
determining a transition from a first activity level of the array to a second activity level of the array; and
selectively controlling the array to minimize the instantaneous current change from the transition from the first activity level to the second activity level; wherein selectively controlling the array comprises controlling a frequency of a core clock for the processor; and controlling the frequency of the core clock comprises first decreasing the frequency of the core clock and then incrementally increasing the frequency of the core clock; and the first activity level is an idle state and the second activity level is an active state.

2. The method of claim 1 , wherein:
determining the transition comprises predicting a future change from the first activity level to the second activity level.

3. The method of claim 1 , wherein:
determining the transition comprises determining a present change from the first activity level to the second activity level;
the array comprises a plurality of portions, each portion comprising a set of the computing elements; and
selectively controlling the array comprises incrementally transitioning each of the plurality of portions of the array from the first activity level to the second activity level until all of the plurality of portions are in the second activity level.

4. The method of claim 3 , wherein:
transitioning each of the plurality of portions of the array from the first activity level to the second activity level comprises providing operands to the computing elements of one or more of the plurality of portions of the array, the operands causing the computing elements to execute.

5. The method of claim 4 , wherein the operands causing the computing elements to execute are dummy operands for which no output is recorded, the method further comprising:
once all of the plurality of portions of the array are in the second activity level, providing real operands to all of computing elements of the array.

6. The method of claim 4 , wherein the operands causing the computing elements to execute are real operands, the method further comprising:
delaying the real operands for the portions of the array which have not transitioned to the second activity level; and
re-aligning the timing of the outputs of the computing elements of the portions of the array.

7. A system for controlling an instantaneous current change in a parallel processor, the system comprising:
an array of computing elements of the processor, the computing elements configured to operate independently of each other in parallel;
a controller configured to determine a transition from a first activity level of the array to a second activity level of the array; and
the controller configured to control the array to minimize the instantaneous current change from the transition from the first activity level to the second activity level; the controller further comprises a clock rate controller configured to control the frequency of a core clock of the processor; the clock rate controller is further configured to first decrease the frequency of the core clock and then incrementally increase the frequency of the core clock, wherein the first activity level is an idle state and the second activity level is an active state.

8. The system of claim 7 , wherein:
the controller comprises an activity monitor configured to predict a future change from the first activity level to the second activity level.

9. The system of claim 7 , wherein:
the controller is configured to determine the transition by determining a present change from the first activity level to the second activity level;
the array comprises a plurality of portions, each portion comprising a set of the computing elements; and
the controller is configured to incrementally transition each of the plurality of portions of the array from the first activity level to the second activity level until all of the plurality of portions are in the second activity level.

10. The system of claim 9 , wherein:
the controller is further configured to incrementally transition each of the plurality of portions of the array from the first activity level to the second activity level by providing operands to the computing elements of one or more of the plurality of portions of the array, the operands causing the computing elements to execute.

11. The system of claim 10 , wherein:
the operands causing the computing elements to execute are dummy operands for which no output is recorded; and
the controller is further configured to cause real operands to be provided to all of the computing elements of the array once all of the portions of the array are in the second activity level.

12. The system of claim 10 , wherein the operands causing the computing elements to execute are real operands, the system further comprising:
one or more delay elements configured to delay providing the real operands for the portions of the array which have not transitioned to the second activity level; and
an output element configured to re-align the timing of the outputs of the computing elements of the portions of the array while portions of the array have not transitioned to the second activity level.

13. The system of claim 7 , wherein the parallel processor is a neural processor.

14. A system for controlling an instantaneous current change in a parallel processor, the system comprising:
an array of computing elements of the processor, the computing elements configured to operate independently of each other in parallel;
a local memory coupled to the array of computing elements, the local memory configured to buffer a stream of operands provided to the array of computing elements; the local memory is configured to receive a plurality of operands in an order different from an order in which the local memory provides the plurality of operands to the array of computing elements; and
a controller configured to determine, based on movement of the operands through the local memory, a transition from a first activity level of the array to a second activity level of the array; the controller is configured to control the array to minimize the instantaneous current change from the transition from the first activity level to the second activity level, the controller further comprises: an activity monitor which detects the first activity and second activity levels of the array, and a clock rate controller; the clock rate controller configured to control the frequency of a core clock of the processor.

15. The system of claim 14 , wherein:
the local memory comprises an input first-in first-out (FIFO) buffer configured to store the operands; and
the activity monitor is configured to predict a future change from the first activity level to the second activity level based on a fill level of the input FIFO buffer.

16. The system of claim 15 , wherein:
the first activity level is an active state and the second activity level is an idle state; and
the activity monitor is configured to cause the clock rate controller to incrementally decrease the frequency of the core clock in response to a prediction of a transition from the active state to the idle state.

17. The system of claim 16 , further comprising an output FIFO buffer configured to store results provided by the array of com

Assignees

• Qualcomm Inc

Inventors

• Ernewein Kyle
• Podaima Jason Edward
• Perez Francisco
• Daniels John
• Miler Alex
• Gemar Jeffrey
• Hill Rexford Alan
• Xu Haoping

Classifications

• G06F1/324 Primary

  by lowering clock frequency · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F1/3228

  Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands · CPC title

• G06F1/3206

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title