Optical sensor arrangement and method for light sensing

Patent metadata

Field	Value
Publication number	US-11029197-B2
Application number	US-201816626457-A
Country	US
Kind code	B2
Filing date	Jun 8, 2018
Priority date	Jul 10, 2017
Publication date	Jun 8, 2021
Grant date	Jun 8, 2021

Abstract

An optical sensor arrangement has an integrator, a photodiode for providing a current corresponding to a first polarity, a comparator coupled to the integrator for comparing a voltage with a threshold voltage to provide a comparison output, a reference charge circuit and a control unit. The reference charge circuit is coupled to the integrator for selectively providing first charge packages of a first size or second charge packages of a second size. The control unit is configured to control operation in a calibration phase, in an integration phase and in a residual measurement phase. During the calibration phase, the reference charge circuit provides one of the first charge packages and one or more of the second charge packages to the integrator until the comparison output changes. A reference number is determined corresponding to a number of the second charge packages provided. During the integration phase, the photodiode is connected to the integrator and the reference charge circuit provides one of the first charge packages to the integrator in response to a respective change of the comparison output. An integration number corresponding to a number of the changes of the comparison output is determined. During the residual measurement phase that immediately follows the integration phase, the reference charge circuit provides one or more of the second charge packages to the integrator until the comparison output changes. A residual number corresponding to a number of the second charge packages provided is determined.

First claim

The invention claimed is:

1. An optical sensor arrangement comprising
an integrator with an integrator input and an integrator output;
a photodiode for providing a current corresponding to a first polarity;
a comparator with a comparator input coupled to the integrator output, the comparator being configured to compare a voltage at the comparator input with a threshold value for providing a comparison output;
a reference charge circuit that is coupled to the integrator input for selectively providing first charge packages of a first size or second charge packages of a second size, wherein the first charge packages correspond to a second polarity being opposite of the first polarity and the second charge packages correspond to the first polarity; and
a control unit that is configured
to, during a calibration phase, control the reference charge circuit to provide one of the first charge packages to the integrator input and to provide one or more of the second charge packages to the integrator input until the comparison output changes, and to determine a reference number corresponding to a number of the second charge packages provided;
to, during an integration phase, connect the photodiode to the integrator input, to control the reference charge circuit to provide one of the first charge packages to the integrator input in response to a respective change of the comparison output and to determine an integration number corresponding to a number of said changes of the comparison output; and
to, during a residual measurement phase that immediately follows the integration phase control the reference charge circuit to provide one or more of the second charge packages to the integrator input until the comparison output changes, and to determine a residual number corresponding to a number of the second charge packages provided.

2. The arrangement of claim 1 , wherein the control unit is configured to provide a total integration value based on the integration number and a ratio of the residual number and the reference number.

3. The arrangement of claim 1 , wherein the integration phase starts with providing one of the first charge packages to the integrator input.

4. The arrangement of claim 1 , wherein the control unit is configured to, during an initialization phase that immediately precedes the integration phase, preset the integrator input to a voltage corresponding to the threshold value with a tolerance corresponding to less than the second size.

5. The arrangement of claim 4 , wherein the control unit is configured to preset the integrator input during the initialization phase by charging an integration capacitor of the integrator to the threshold value.

6. The arrangement of claim 4 , wherein the control unit is configured to preset the integrator input during the initialization phase by controlling the reference charge circuit to provide one or more of the first charge packages to the integrator input until the comparison output changes a first time, and controlling the reference charge circuit) to provide one or more of the second charge packages to the integrator input until the comparison output changes a second time.

7. The arrangement of claim 1 , wherein
the reference charge circuit comprises a reference capacitor;
for providing the first charge package, the reference capacitor is charged with a first reference voltage while the reference capacitor is disconnected from the integrator input, and after the charging is connected to the integrator input; and
for providing the second charge package, the reference capacitor is charged with a second reference voltage while the reference capacitor is disconnected from the integrator input, and after the charging is connected to the integrator input.

8. The arrangement of claim 1 , wherein
the reference charge circuit comprises a first and a second reference capacitor;
for providing the first charge package, the first reference capacitor is charged with a first reference voltage while the first reference capacitor is disconnected from the integrator input, and after the charging is connected to the integrator input; and
for providing the second charge package, the second reference capacitor is charged with the first reference voltage or with a second reference voltage while the second reference capacitor is disconnected from the integrator input, and after the charging is connected to the integrator input.

9. The arrangement of claim 7 , wherein the charging and the provision of the first and second charge packages are based on a reference clock signal.

10. The arrangement of claim 9 , wherein a clock speed of the reference clock signal is reduced during the calibration phase and/or the residual measurement phase, in particular compared to the integration phase.

11. The arrangement of claim 1 , wherein an amplifier of the integrator is operated in a lower noise mode of operation during the calibration phase and/or the residual measurement phase, in particular compared to the integration phase.

12. The arrangement of claim 1 , wherein the control unit is configured to enter the calibration phase more than once, and to determine a mean value from the respective reference numbers determined in each of said calibration phases, said mean value being used as a final reference number.

13. The arrangement of claim 1 , wherein the first size of the first charge package is trimmed and the second size of the second charge package is not trimmed.

14. A light sensing method to be performed with an arrangement having a photodiode providing a current corresponding to a first polarity, an integrator with an integrator input and an integrator output, and a comparator with a comparator input coupled to the integrator output, the comparator being configured to compare a voltage at the comparator input with a threshold value for providing a comparison output, the method comprising:
during a calibration phase, provide one of first charge packages of a first size to the integrator input and provide one or more of second charge packages of a second size to the integrator input until the comparison output changes, and determine a reference number corresponding to a number of the second charge packages provided, wherein the first charge packages correspond to a second polarity being opposite of the first polarity and the second charge packages correspond to the first polarity;
during an integration phase, connect the photodiode to the integrator input, provide one of the first charge packages to the integrator input in response to a respective change of the comparison output and determine an integration number corresponding to a number of said changes of the comparison output; and
during a residual measurement phase that immediately follows the integration phase, provide one or more of the second charge packages to the integrator input until the comparison output changes, and to determine a residual number corresponding to a number of the second charge packages provided.

15. The method of claim 14 , wherein during an initialization phase that immediately precedes the integration phase, the integrator input is preset to a voltage corresponding to the threshold value with a tolerance corresponding to less than the second size.

Assignees

• Ams Ag

Inventors

• Greimel-Längauer Bernhard
• Bliem Peter

Classifications

• G01J1/46

  using a capacitor · CPC title

• G01J1/18 Primary

  using comparison with a reference electric value · CPC title

• G01J2001/446

  Photodiode · CPC title

• G01J2001/444

  Compensating; Calibrating, e.g. dark current, temperature drift, noise reduction or baseline correction; Adjusting · CPC title

• G01J2001/4426

  with intensity to frequency or voltage to frequency conversion [IFC or VFC] · CPC title