Systems and methods for integration of injection-locked oscillators into transceiver arrays

US11025258B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11025258-B2
Application numberUS-201916598925-A
CountryUS
Kind codeB2
Filing dateOct 10, 2019
Priority dateOct 12, 2018
Publication dateJun 1, 2021
Grant dateJun 1, 2021

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Systems and methods for integrating injection-locked oscillators into transceiver arrays are disclosed. In one aspect, there is provided an injection-locked oscillator (ILO) distribution system including a master clock generator configured to generate a master clock signal. The ILO distribution system also includes an ILO distribution circuit including an ILO and configured to receive the master clock signal. The ILO is configured to generate a reference clock signal based on the master clock signal. The ILO distribution circuit is further configured to generate an output signal indicative of an operating frequency of the ILO. The ILO distribution system further includes an injection-locked detector (ILD) configured to receive the master clock signal and the output signal. The ILD is further configured to determine whether the ILO is in a locked state or in an unlocked state based on the master clock signal and the output signal.

First claim

Opening claim text (preview).

What is claimed is: 1. An injection-locked oscillator distribution system, comprising: a master clock generator configured to generate a master clock signal; an injection-locked oscillator distribution circuit including an injection-locked oscillator and configured to receive the master clock signal, the injection-locked oscillator configured to generate a reference clock signal based on the master clock signal and having a higher frequency than the master clock signal, the injection-locked oscillator distribution circuit further configured to generate an output signal indicative of an operating frequency of the injection-locked oscillator via down-converting the reference clock signal to a frequency of the master clock signal; and an injection-locked detector configured to receive the master clock signal and the output signal, the injection-locked detector further configured to determine whether the injection-locked oscillator is in a locked state or in an unlocked state based on the master clock signal and the output signal. 2. The injection-locked oscillator distribution system of claim 1 wherein the injection-locked oscillator distribution circuit further includes a mixer configured to generate the output signal. 3. The injection-locked oscillator distribution system of claim 1 wherein the injection-locked oscillator distribution circuit further includes divider circuitry configured to generate the output signal. 4. An injection-locked oscillator distribution system, comprising: master clock generator configured to generate a master clock signal; an injection-locked oscillator distribution circuit including an injection-locked oscillator and configured to receive the master clock signal, the injection-locked oscillator configured to generate a reference clock signal based on the master clock signal, the injection-locked oscillator distribution circuit further configured to generate an output signal indicative of an operating frequency of the injection-locked oscillator, the injection-locked oscillator distribution circuit operatively coupled to a mixer of a transceiver circuit, the injection-locked oscillator distribution circuit further configured to provide the reference clock signal to the mixer of the transceiver circuit; and an injection-locked detector configured to receive the master clock signal and the output signal, the injection-locked detector further configured to determine whether the injection-locked oscillator is in a locked state or in an unlocked state based on the master clock signal and the output signal. 5. The injection-locked oscillator distribution system of claim 4 wherein the injection-locked detector includes a mixer configured to mix the output signal with the master clock signal to generate an intermediate mixed signal, the injection-locked detector further configured to determine whether the injection-locked oscillator is in the locked state or in the unlocked state based on the intermediate mixed signal. 6. The injection-locked oscillator distribution system of claim 5 wherein the injection-locked detector includes a low-pass filter configured to receive the intermediate mixed signal and generate an intermediate voltage, the injection-locked detector further including a comparator configured to compare the intermediate voltage to a reference voltage and output a signal indicative of whether the injection-locked oscillator is in the locked state or in the unlocked state based on the comparison of the intermediate voltage to the reference voltage. 7. The injection-locked oscillator distribution system of claim 4 further including an additional injection-locked oscillator distribution circuit, the injection-locked detector further including selection logic configured to select one of the output signal and an additional output signal from the additional injection-locked oscillator. 8. The injection-locked oscillator distribution system of claim 4 wherein injection-locked oscillator is further configured to generate the reference clock signal having a higher frequency than the master clock signal and the injection-locked oscillator distribution circuit is further configured to generate the output signal via down-converting the reference clock signal to a frequency of the master clock signal. 9. A method of detecting an injection-locked state, comprising: generating, by a master clock generator, a master clock signal; receiving, at an injection-locked oscillator distribution circuit, the master clock signal, the injection-locked oscillator distribution circuit including an injection-locked oscillator; generating, at the injection-locked oscillator, a reference clock signal based on the master clock signal; generating, at the injection-locked oscillator distribution circuit, an output signal indicative of an operating frequency of the injection-locked oscillator; receiving, at an injection-locked detector, the master clock signal and the output signal; mixing, at a mixer included in the injection-locked detector, the output signal with the master clock signal to generate an intermediate mixed signal; and determining, by the injection-locked detector, whether the injection-locked oscillator is in a locked state or in an unlocked state based on the intermediate mixed signal. 10. The method of claim 9 further comprising: generating, at the injection-locked oscillator, the reference clock signal having a higher frequency than the master clock signal; and generating, at the injection-locked oscillator distribution circuit, the output signal via down-converting the reference clock signal to a frequency of the master clock signal. 11. The method of claim 10 further comprising generating the output signal at a mixer of the injection-locked oscillator distribution circuit. 12. The method of claim 10 further comprising generating the output signal at divider circuitry the injection-locked oscillator distribution circuit. 13. The method of claim 9 further comprising: generating, at a low-pass filter of the injection-locked detector, an intermediate voltage based on the intermediate mixed signal; comparing, at a comparator of the injection-locked detector, the intermediate voltage to a reference voltage; and outputting, at the comparator, a signal indicative of whether the injection-locked oscillator is in the locked state or in the unlocked state based on the comparison of the intermediate voltage to the reference voltage. 14. The method of claim 9 further comprising selecting, at selection logic, one of the output signal and an additional output signal received from an additional injection-locked oscillator. 15. The method of claim 9 further comprising providing reference clock signal to a mixer of a transceiver circuit. 16. A mobile device, comprising: an antenna; a transceiver circuit operatively coupled to the antenna, the transceiver including a first mixer; a master clock generator configured to generate a master clock signal; an injection-locked oscillator distribution circuit including an injection-locked oscillator and configured to receive the master clock signal, the injection-locked oscillator operatively coupled to the first mixer and configured to generate a reference clock signal based on the master clock signal and provide the reference clock signal to the first mixer, the injection-locked oscillator distribution circuit further configured to generate an output signal indicative of an operating frequency of the injection-locked oscillator; and an injection-locked detector configured to receive the master clock signal and the output sig

Assignees

Inventors

Classifications

  • Locking of an oscillator by injecting an input signal directly into the oscillator · CPC title

  • adapting radio receivers, transmitters andtransceivers for operation on two or more bands, i.e. frequency ranges · CPC title

  • Distribution of clock signals {, e.g. skew} · CPC title

  • G06F1/06Primary

    Clock generators producing several clock signals {(G06F1/08 - G06F1/14 take precedence)} · CPC title

  • H03L7/0816Primary

    the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input · CPC title

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What does patent US11025258B2 cover?
Systems and methods for integrating injection-locked oscillators into transceiver arrays are disclosed. In one aspect, there is provided an injection-locked oscillator (ILO) distribution system including a master clock generator configured to generate a master clock signal. The ILO distribution system also includes an ILO distribution circuit including an ILO and configured to receive the maste…
Who is the assignee on this patent?
Skyworks Solutions Inc
What technology area does this patent fall under?
Primary CPC classification G06F1/06. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jun 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 7 related publications on this page (citations in our corpus or others sharing the same primary CPC).