Signal processing apparatus, motor, and fan motor

Patent metadata

Field	Value
Publication number	US-11025182-B2
Application number	US-201916669651-A
Country	US
Kind code	B2
Filing date	Oct 31, 2019
Priority date	Nov 27, 2018
Publication date	Jun 1, 2021
Grant date	Jun 1, 2021

Abstract

A signal processing apparatus includes a processor, a memory storing a program, and an integration circuit that performs filter processing on an input signal to output a processed signal. The processor samples an output signal output from the integration circuit in a sampling period Ts and stores a sampled value of the output signal in accordance with the program, and detects a duty of the input signal based on a difference between a value of the output signal at a time t0 representing a present time point and a sampled value of the output signal obtained at a time t0−n representing an earlier time than the time t0 by an n sampling period when n is a positive integer, the value of the output signal, a value of the integer n, the sampling period Ts, and a time constant of a filter of the integration circuit.

First claim

What is claimed is:

1. A signal processing apparatus comprising:
a processor;
a memory that stores a program that controls operation of the processor; and
an integration circuit to perform filter processing on an input signal and output a output signal; wherein
in accordance with the program stored in the memory, the processor:
samples the output signal output from the integration circuit in response to the input signal in a predetermined sampling period Ts and stores a sampled value of the output signal in the memory; and
detects a duty D of the input signal based on:
a difference between a value of the output signal output from the integration circuit at a time t 0 representing a present time point and a sampled value of the output signal which is obtained at a time t 0 −n representing an earlier time than the time t 0 by an n sampling period when n is a positive integer;
the value of the output signal from the integration circuit;
a value of the integer n;

the sampling period Ts; and
a time constant τ of a filter of the integration circuit; and

the processor detects the duty D of the input signal by adding a value obtained by multiplying the difference by a ratio τ/Ts of the time constant τ of the filter to the sampling period Ts and 1/n, to the value of the output signal from the integration circuit.

2. The signal processing apparatus according to claim 1 , wherein the processor detects the duty D of the input signal by calculating:
D=s ( t 0 )+(1/ n ){ s ( t 0 )− s ( t 0 −n )}(τ/ Ts ),

where s(t 0 ) denotes the value of the output signal output from the integration circuit at the time t 0 , and s(t 0 −n) denotes the sampled value of the output signal obtained at the time t 0 −n.

3. The signal processing apparatus according to claim 1 , wherein the processor detects the duty D of the input signal by calculating:
D=s ( t 0 −n )+(1/ n ){ s ( t 0 )− s ( t 0 −n )}(τ/ Ts ),

where s(t 0 ) denotes the value of the output signal output from the integration circuit at the time t 0 , and s(t 0 −n) denotes the sampled value of the output signal obtained at the time t 0 −n.

4. The signal processing apparatus according to claim 1 , wherein the processor detects the duty D of the input signal by calculating:
D={s ( t 0 )+ s ( t 0 −n )}/2+(1/ n ){ s ( t 0 )− s ( t 0 −n )}(τ/ Ts ),

where s(t 0 ) denotes the value of the output signal output from the integration circuit at the time t 0 , and s(t 0 −n) denotes the sampled value of the output signal at the time t 0 −n.

5. The signal processing apparatus according to claim 1 , wherein the sampling period Ts is about ⅕ or smaller the time constant τ of the filter.

6. The signal processing apparatus according to claim 1 , wherein the input signal is a pulse width modulation signal.

7. The signal processing apparatus according to claim 6 , wherein the time constant τ of the filter is determined based on a period of the pulse width modulation signal.

8. The signal processing apparatus according to claim 7 , wherein the time constant τ of the filter is 100 times or larger the period of the pulse width modulation signal.

9. The signal processing apparatus according to claim 1 , wherein the value of the integer n is 1.

10. A motor comprising:
the signal processing apparatus according to claim 1 ;
a stator; and
a rotor.

11. The motor according to claim 10 , wherein
the motor includes an operation mode that can be switched to a communication mode used in communicating with an external device; and
the operation mode is switched to the communication mode in response to continuous detection of the input signal with the duty D within a range for a predetermined period.

12. The motor according to claim 10 , wherein motor control is performed by using the duty D of the input signal detected by the signal processing apparatus and the output signal output from the integration circuit.

13. A fan motor comprising:
an impeller;
a motor; and
the signal processing apparatus according to claim 1 .

Assignees

• Nidec Corp

Inventors

• Takemoto Hideyuki

Classifications

• H03K5/19 Primary

  Monitoring patterns of pulse trains (indicating amplitude G01R19/00; indicating frequency G01R23/00; measuring characteristics of individual pulses G01R29/02) · CPC title

• G01R29/02

  Measuring characteristics of individual pulses, e.g. deviation from pulse flatness, rise time or duration · CPC title

• H02P7/29 Primary

  using pulse modulation · CPC title

• H03M13/156 Primary

  Encoding or decoding using time-frequency transformations, e.g. fast Fourier transformation · CPC title

• H02P6/08

  Arrangements for controlling the speed or torque of a single motor (H02P6/10, H02P6/28 take precedence) · CPC title