Reducing parasitic capacities in a microelectronic device

Patent metadata

Field	Value
Publication number	US-11024795-B2
Application number	US-201716467617-A
Country	US
Kind code	B2
Filing date	Dec 8, 2017
Priority date	Dec 12, 2016
Publication date	Jun 1, 2021
Grant date	Jun 1, 2021

Abstract

A microelectronic device including a substrate including, in a stack, a base portion, a dielectric portion and an upper layer with a semi-conductive material base, at least one electrical connection element made of an electrically conductive material located above the upper layer and electrically insulated from the upper layer at least by a dielectric layer, the dielectric layer being in contact with the surface of the upper layer, at least one dielectric element including at least one trench forming a closed edge at the periphery or upright of at least one portion of the dielectric electrical connection element, located at least partially in the upper layer and delimiting a closed zone of said upper layer, at least one dielectric element having a portion exposed to the surface of the upper layer, device wherein the dielectric layer totally covers the exposed portion of at least one dielectric element.

First claim

The invention claimed is:

1. A microelectronic device, comprising:
a substrate comprising, in a stack, a base portion, a dielectric portion, and an upper layer with a semi-conductive material base;
at least one electrical connection element made of an electrically conductive material located above the upper layer and electrically insulated from the upper layer at least by a dielectric layer, the dielectric layer being in contact with a surface of the upper layer; and
at least one dielectric element comprising at least one trench forming a closed edge at a periphery or upright of at least one portion of the at least one electrical connection element, located at least partially in the upper layer and delimiting a closed zone of said upper layer, the at least one dielectric element having a portion exposed to the surface of the upper layer,
wherein the dielectric layer totally covers the exposed portion of the at least one dielectric element.

2. The device according to claim 1 , wherein the at least one dielectric element and the dielectric layer are made of different materials.

3. The device according to claim 2 , wherein the at least one dielectric element is made of silicon dioxide, and wherein the dielectric layer is resistant to a hydrofluoric acid etching.

4. The device according to claim 1 , wherein the at least one electrical connection element is in electrical continuity with a first electrode of a capacitive stack.

5. The device according to claim 4 , wherein the capacitive stack comprises a second electrode located below a portion of the dielectric layer, at least one portion of the first electrode being located facing the second electrode and insulated from the second electrode by said portion of the dielectric layer.

6. The device according to claim 5 , wherein a dielectric sublayer is located between the upper layer and the second electrode.

7. The device according to claim 5 , further comprising an additional electrical connection element made of an electrically conductive material located above the upper layer and electrically insulated from the upper layer at least by a zone of the dielectric layer, the additional electrical connection element being in electrical continuity with the second electrode by a via passing through the dielectric layer.

8. The device according to claim 1 , wherein the dielectric layer is of piezoelectric nature.

9. The device according to claim 1 , wherein the at least one dielectric element further comprises at least one pillar of which a long dimension extends according to at least one portion of a thickness of the upper layer.

10. The device according to claim 9 , wherein the at least one pillar is located facing the at least one electrical connection element under the dielectric layer.

11. The device according to claim 1 , wherein the at least one dielectric element further comprises a network of trenches defined as hollow in a thickness of the upper layer around a plurality of pillars extending at least into the thickness of the upper layer.

12. The device according to claim 11 , wherein at least one pillar of the plurality of pillars is located facing the at least one electrical connection element under the dielectric layer.

13. The device according to claim 9 , wherein at least one trench surrounds the at least one pillar.

14. The device according to claim 1 , wherein the at least one dielectric element further comprises a plurality of trenches.

15. The device according to claim 1 , wherein the at least one dielectric element further comprises a first portion located in the upper layer and a second portion located above the upper layer.

16. The device according to claim 1 , wherein the at least one electrical connection element comprises a connection pad.

17. The device according to claim 1 , wherein the dielectric layer is wider than the at least one electrical connection element, and wherein the at least one dielectric element is located facing a portion of the dielectric layer not covered by the at least one connection element.

18. The device according to claim 1 , wherein the at least one dielectric element passes through a whole thickness of the upper layer and joins the dielectric portion.

19. A method for producing a microelectronic device comprising a substrate comprising, in a stack, a base portion, a dielectric portion, and an upper layer with a semi-conductive material base, the method comprising:
forming at least one dielectric element located at least partially in the upper layer, the at least one dielectric element having a portion exposed to a surface of the upper layer, the at least one dielectric element comprising at least one trench delimiting a closed zone of the upper layer, at a periphery or upright of at least one portion of the at least one electrical connection element;
forming a dielectric layer in contact with the surface of the upper layer and which totally covers the exposed portion of the at least one dielectric element; and
forming at least one electrical connection element made of an electrically conductive material above the upper layer and electrically insulated from the upper layer at least by the dielectric layer.

20. The method according to claim 19 , further comprising forming at least one zone made of a sacrificial material in the upper layer, then etching the sacrificial material, while the at least one dielectric element is covered by the dielectric layer.

21. The method according to claim 20 , wherein the forming of the at least one zone made of the sacrificial material is carried out before the forming of the dielectric layer, simultaneously to the forming of the at least one dielectric element.

22. The method according to claim 21 , wherein the forming of the dielectric layer comprises a solid plate deposition, then an etching configured to preserve a material of the dielectric layer above the at least one dielectric element without preserving the material of the dielectric layer above the at least one zone made of the sacrificial material.

Assignees

• Commissariat Energie Atomique

Inventors

• Robert Philippe
• Louwers Stephanus

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/061

  using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10P90/1906

  Preparing SOI wafers · CPC title