Laterally diffused MOSFET with low Rsp*Qg product

Patent metadata

Field	Value
Publication number	US-11024733-B2
Application number	US-202016887776-A
Country	US
Kind code	B2
Filing date	May 29, 2020
Priority date	Sep 13, 2018
Publication date	Jun 1, 2021
Grant date	Jun 1, 2021

Abstract

An improved laterally diffused MOSFET (LDMOS) device enables an ability to tune some device parameters independently of other device parameters and/or provides a device architecture with component dimensions that significantly improve device performance. The LDMOS device includes a stepped gate having a first portion with a thin gate insulator over a body region and a second portion with a thick gate insulator over part of a drift region. In some embodiments, a gate shield is disposed over another part of the drift region to reduce a gate-drain capacitance of the LDMOS device. In some embodiments, the LDMOS device has a specific resistance (Rsp) of about 5-8 mOhm*mm2, a gate charge (Qg) of about 1.9-2.0 nC/mm2, and an Rsp*Qg product figure of merit of about 10-15 mOhm*nC.

First claim

What is claimed is:

1. A laterally diffused MOSFET device comprising:
a source region in an active layer;
a drain region in the active layer;
a body region in the active layer between the source region and the drain region;
a drift region in the active layer between the body region and the drain region, wherein the drift region extends to a top surface of the active layer for an entire lateral extent between the body region and the drain region without a shallow trench isolation region or a local oxidation of silicon isolation region between the body region and the drain region;
a stepped gate having a first portion disposed over the body region and a second portion disposed over a first portion of the drift region, the first and second portions of the stepped gate being continuous with each other;
a first gate insulator region between the first portion of the stepped gate and the body region, the first gate insulator region having a first thickness;
a second gate insulator region between the second portion of the stepped gate and the first portion of the drift region, the second gate insulator region having a second thickness greater than the first thickness; and
a gate shield, a first portion of which is disposed over a second portion of the drift region between the stepped gate and the drain region to reduce a gate-drain capacitance of the laterally diffused MOSFET device.

2. The laterally diffused MOSFET device of claim 1 , wherein:
the laterally diffused MOSFET device has a specific resistance (Rsp) of about 5-8 mOhm*mm 2 and a gate charge (Qg) of about 1.5-3.0 nC/mm 2 .

3. The laterally diffused MOSFET device of claim 2 , wherein:
the laterally diffused MOSFET device further has an Rsp*Qg product figure of merit of about 10-15 mOhm*nC.

4. The laterally diffused MOSFET device of claim 3 , wherein:
the first portion of the stepped gate has a first length of about 0.1-0.4 μm;
the second portion of the stepped gate has a second length of about 0.1-0.6 μm;
the first gate insulator region has a first thickness of about 30-62 Å; and
the second gate insulator region has a second thickness of about 300-500 Å.

5. The laterally diffused MOSFET device of claim 4 , further comprising:
a shield insulator region between the first portion of the gate shield and the second portion of the drift region, the shield insulator region having a thickness of about 900-1100 Å;
wherein the gate shield laterally extends about 0.3-0.7 μm from above an edge of the stepped gate in a direction toward the drain region.

6. The laterally diffused MOSFET device of claim 5 , wherein:
the laterally diffused MOSFET device is configured to form a channel region within the body region having a length that is about the same as the first length of the first portion of the stepped gate; and
the laterally diffused MOSFET device is configured to form an accumulation region within the first portion of the drift region due to an electric field from the second portion of the stepped gate.

7. The laterally diffused MOSFET device of claim 6 , wherein:
the channel region is aligned with the first portion of the stepped gate.

8. The laterally diffused MOSFET device of claim 1 , further comprising:
a source contact electrically connected to the source region and to the gate shield.

9. The laterally diffused MOSFET device of claim 1 , wherein:
a second portion of the gate shield is disposed over the stepped gate.

10. An electronic circuit comprising the laterally diffused MOSFET device of claim 1 , the electronic circuit further comprising:
a switching element electrically connected to a phase node, the switching element comprising the laterally diffused MOSFET device;
a controller electrically connected to the laterally diffused MOSFET device to provide a drive signal to the stepped gate;
an inductor electrically connected to the phase node and an output node; and
a load electrically connected to receive an output voltage at the output node.

11. The electronic circuit of claim 10 , wherein:
the controller is operable to provide the drive signal to the stepped gate with a switching frequency of about 1-8 MHz.

12. A laterally diffused MOSFET device comprising:
a source region;
a drain region;
a body region between the source region and the drain region;
a drift region between the body region and the drain region;
a stepped gate having a first portion and a second portion adjacent to and continuous with each other;
a first gate insulator region between the first portion of the stepped gate and the body region; and
a second gate insulator region between the second portion of the stepped gate and at least a first portion of the drift region;
wherein:
the laterally diffused MOSFET device has an Rsp*Qg product figure of merit of about 10-15 mOhm*nC.

13. The laterally diffused MOSFET device of claim 12 , wherein:
the laterally diffused MOSFET device further has a specific resistance (Rsp) of about 5-8 mOhm*mm 2 , and a gate charge (Qg) of about 1.5-3.0 nC/mm 2 .

14. The laterally diffused MOSFET device of claim 12 , further comprising:
a gate shield, a first portion of the gate shield being disposed over a second portion of the drift region between the stepped gate and the drain region, and a second portion of the gate shield being disposed over the stepped gate, the gate shield being configured to reduce a gate-drain capacitance of the laterally diffused MOSFET device.

15. The laterally diffused MOSFET device of claim 12 , wherein:
the first portion of the stepped gate has a first length of about 0.1-0.4 μm;
the second portion of the stepped gate has a second length of about 0.1-0.6 μm;
the first gate insulator region has a first thickness of about 30-62 Å; and
the second gate insulator region has a second thickness of about 300-500 Å.

16. An electronic circuit comprising the laterally diffused MOSFET device of claim 12 , the electronic circuit further comprising:
a switching element electrically connected to a phase node, the switching element comprising the laterally diffused MOSFET device;
a controller electrically connected to the laterally diffused MOSFET device to provide a drive signal to the stepped gate;
an inductor electrically connected to the phase node and an output node; and
a load electrically connected to receive an output voltage at the output node.

17. The electronic circuit of claim 16 , wherein:
the drive signal is provided to the stepped gate with a switching frequency of about 1-8 MHz.

18. The laterally diffused MOSFET device of claim 12 , further comprising:
a first gate-drain capacitance between the first portion of the stepped gate and the drift region;
a second gate-drain capacitance between the second portion of the stepped gate and the drift region; and
a third gate-drain capacitance between the stepped gate and a drain contact that is almost zero.

19. The laterally diffused MOSFET device of claim 12 , further comprising:
a channel region being aligned with, and having about a same length as, the first portion of the stepped gate; and
an accumulation region within the first portion of the drift region due to an electric field from the second portion of the stepped gate.

20. The laterally diffused MOSFET device of claim 12 , wherein:
the drift region and the body region are formed above a buried insulator layer of an SOI wafer.

Assignees

• Silanna Asia Pte Ltd

Inventors

• Snyder David

Classifications

• H10D30/0281

  of lateral DMOS [LDMOS] FETs · CPC title

• H10D64/514

  characterised by the insulating layers · CPC title

• H10D84/0144

  Manufacturing their gate insulating layers · CPC title

• H10D84/0147

  Manufacturing their gate sidewall spacers · CPC title

• H10D30/65 Primary

  Lateral DMOS [LDMOS] FETs · CPC title