Nanowire transistor fabrication with hardmask layers

Patent metadata

Field	Value
Publication number	US-11024714-B2
Application number	US-201816149056-A
Country	US
Kind code	B2
Filing date	Oct 1, 2018
Priority date	Mar 15, 2013
Publication date	Jun 1, 2021
Grant date	Jun 1, 2021

Abstract

A nanowire device of the present description may be produced with the incorporation of at least one hardmask during the fabrication of at least one nanowire transistor in order to assist in protecting an uppermost channel nanowire from damage that may result from fabrication processes, such as those used in a replacement metal gate process and/or the nanowire release process. The use of at least one hardmask may result in a substantially damage free uppermost channel nanowire in a multi-stacked nanowire transistor, which may improve the uniformity of the channel nanowires and the reliability of the overall multi-stacked nanowire transistor.

First claim

What is claimed is:

1. A method of forming a microelectronic structure, comprising:
forming a fin structure on a microelectronic substrate, wherein the fin structure comprises at least one sacrificial material layer alternating with at least one channel material layer, and hardmask layer on a top surface of the channel material layer farthest from the microelectronic substrate;
forming at least two spacers across the fin structure;
selectively removing the sacrificial material layers between the channel material layers to form at least one channel nanowire, wherein the hardmask layer protects the uppermost channel material layer during the selectively removing the sacrificial material layers;
removing the hardmask layer from between the spacers after selectively removing the sacrificial material layers between the channel material layers to leave a portion of the hardmask layer between the spacers and a channel nanowire top surface farthest from the microelectronic substrate.

2. The method of claim 1 , wherein forming the fin structure on the microelectronic substrate, wherein the fin structure comprises at least one sacrificial material layer alternating with at least one channel material layer, and hardmask layer on the top surface of the channel material layer farthest from the microelectronic substrate, comprises:
forming a microelectronic substrate;
forming a stacked layer comprising at least one sacrificial material layer alternating with at least one channel material layer;
forming a hardmask layer on a top surface of the channel material layer farthest from the microelectronic substrate; and
forming at least one fin structure from the layered stack and the hardmask layer.

3. The method of claim 1 , further including:
forming a sacrificial gate electrode material between the at least two spacers;
removing a portion fin structure external to the sacrificial gate electrode material and the spacers to expose portions of the microelectronic substrate; and
forming a source structure and a drain structure on the substrate portions on opposing ends of the fin structure.

4. The method of claim 3 , further including:
forming an interlayer dielectric layer over the source structure and the drain structure;
and removing the sacrificial gate electrode material from between the spacers prior to selectively removing the sacrificial material layers between the channel material layers to form the at least one channel nanowire.

5. The method of claim 4 , further including:
forming a gate dielectric material to surround the channel nanowire between the spacers; and
forming a gate electrode material on the gate dielectric material.

6. The method of claim 1 , wherein forming a hardmask layer on a top surface of the channel material layer farthest from the microelectronic substrate comprises forming a hardmask layer from a material selected from the group comprising silicon, porous silicon, amorphous silicon, silicon nitride, silicon oxynitride, silicon oxide, silicon dioxide, silicon carbonitride, silicon carbide, aluminum oxide, hafnium oxide, zirconium oxide, tantalum silicate, lanthanum oxide, and polymer materials.

7. A method of forming a microelectronic structure, comprising:
forming a microelectronic substrate;
forming a stacked layer comprising at least one sacrificial material layer alternating with at least one channel material layer;
forming a first hardmask layer on a top surface of the channel material layer farthest from the microelectronic substrate;
forming a second hardmask layer on the first hardmask layer;
forming at least one fin structure from the layered stack, the first hardmask layer, and the second hardmask layer;
removing the second hardmask layer; forming at least two spacers across the fin structure;
selectively removing the sacrificial material layers between the channel material layers to form at least one channel nanowire, wherein the hardmask layer protects the uppermost channel material layer during the selectively removing the sacrificial material layers;
removing the first hardmask layer from between the spacers after selectively removing the sacrificial material layers between the channel material layers to leave a portion of the first hardmask layer between the spacers and a channel nanowire top surface farthest from the microelectronic substrate.

8. The method of claim 7 , further including:
forming a sacrificial gate electrode material between the at least two spacers;
removing a portion fin structure external to the sacrificial gate electrode material and the spacers to expose portions of the microelectronic substrate; and
forming a source structure and a drain structure on the substrate portions on opposing ends of the fin structure.

9. The method of claim 8 , further including:
forming an interlayer dielectric layer over the source structure and the drain structure;

and removing the sacrificial gate electrode material from between the spacers prior to selectively removing the sacrificial material layers between the channel material layers to form the at least one channel nanowire.

10. The method of claim 7 , further including:
forming a gate dielectric material to surround the channel nanowire between the spacers; and
forming a gate electrode material on the gate dielectric material.

11. The method of claim 7 , wherein forming the first hardmask layer on a top surface of the channel material layer farthest from the microelectronic substrate comprises forming the hardmask layer from a material selected from the group comprising silicon, porous silicon, amorphous silicon, silicon nitride, silicon oxynitride, silicon oxide, silicon dioxide, silicon carbonitride, silicon carbide, aluminum oxide, hafnium oxide, zirconium oxide, tantalum silicate, lanthanum oxide, and polymer materials.

12. The method of claim 7 , wherein forming the second hardmask layer on first hardmask layer comprises forming the second hardmask layer from a material selected from the group comprising silicon, porous silicon, amorphous silicon, silicon nitride, silicon oxynitride, silicon oxide, silicon dioxide, silicon carbonitride, silicon carbide, aluminum oxide, hafnium oxide, zirconium oxide, tantalum silicate, lanthanum oxide, and polymer materials.

13. A method for forming a nanowire transistor, comprising:
forming a plurality of nanowire channels above a microelectronic substrate, wherein each nanowire channel of the plurality of the nanowire channels are spaced apart from one another by first providing at least one sacrificial material layer alternating with at least one channel material layer and selectively removing the sacrificial material layers between the channel material layers, and wherein one nanowire channel of the plurality of nanowire channels is positioned farther from the microelectronic substrate than the remainder of the plurality of nanowire channels;
forming a source abutting a first end of each nanowire channel of the plurality of nanowire channels;
forming a drain abutting a second end of each nanowire channel of the plurality of nanowire channels;
forming a first spacer positioned proximate the first end of each nanowire channel of the plurality of nanowire channels and forming a second spacer positioned proximate the second end of each nanowire channel of the plurality of nanowire channels, wherein the first spacer physically contacts each nanowire channel of the plurality of nanowire channels and wherein the second spacer physically contacts each nanowire channel of the plurality of nanowire channels;
forming a hardmask layer comprising a first hardmask portion and a second hardmask

Assignees

• Sony Corp

Inventors

• Sung Seung Hoon
• Kim Seiyon
• Kuhn Kelin J
• Rachmady Willy
• Kavalieros Jack T

Classifications

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H10D64/021

  using multiple gate spacer layers, e.g. bilayered sidewall spacers · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title