Manufacturing method of capacitor structure

Patent metadata

Field	Value
Publication number	US-11024704-B1
Application number	US-202016802481-A
Country	US
Kind code	B1
Filing date	Feb 26, 2020
Priority date	Feb 5, 2020
Publication date	Jun 1, 2021
Grant date	Jun 1, 2021

Abstract

A manufacturing method of a capacitor structure includes the following steps. A first capacitor is formed on a substrate. The first capacitor includes a first electrically conductive pattern and a second electrically conductive pattern of a first electrically conductive layer and a first dielectric layer disposed therebetween in a horizontal direction. A second capacitor is formed on the substrate before forming the first capacitor. The second capacitor includes a third electrically conductive pattern and a fourth electrically conductive pattern of a second electrically conductive layer and a second dielectric layer disposed therebetween in the horizontal direction. A thickness of the second electrically conductive layer is monitored. A target value of a thickness of the first electrically conductive layer is controlled in accordance with a value of a monitored thickness of the second electrically conductive layer.

First claim

What is claimed is:

1. A manufacturing method of a capacitor structure, comprising:
forming a first capacitor on a substrate, wherein the first capacitor comprises:
a first electrically conductive pattern of a first electrically conductive layer;
a second electrically conductive pattern of the first electrically conductive layer; and
a first dielectric layer disposed between the first electrically conductive pattern and the second electrically conductive pattern in a horizontal direction;

forming a second capacitor on the substrate before the step of forming the first capacitor, wherein the second capacitor comprises:
a third electrically conductive pattern of a second electrically conductive layer;
a fourth electrically conductive pattern of the second electrically conductive layer; and
a second dielectric layer disposed between the third electrically conductive pattern and the fourth electrically conductive pattern in the horizontal direction;

monitoring a thickness of the second electrically conductive layer; and
controlling a target value of a thickness of the first electrically conductive layer in accordance with a value of a monitored thickness of the second electrically conductive layer.

2. The manufacturing method of the capacitor structure according to claim 1 , wherein the first capacitor and the second capacitor comprise a metal-oxide-metal (MOM) capacitor respectively.

3. The manufacturing method of the capacitor structure according to claim 1 , wherein the controlling the target value of the thickness of the first electrically conductive layer comprises:
adjusting the target value of the thickness of the first electrically conductive layer when the value of the monitored thickness of the second electrically conductive layer is out of a predetermined range; and
keeping the target value of the thickness of the first electrically conductive layer unchanged when the value of the monitored thickness of the second electrically conductive layer is within the predetermined range.

4. The manufacturing method of the capacitor structure according to claim 3 , wherein the first capacitor is the nth capacitor unit of a plurality of capacitor units stacked on the substrate, the first electrically conductive layer is the nth metal layer of a plurality of metal layers stacked on the substrate, and a target value of a thickness of the nth metal layer is calculated by a following equation:

T

3
⁢
n

=

R
⁢

S
n

-

∑

k
=
1

n
-
1

⁢

X
k

×

T

2
⁢
k

×

C

2
⁢
k

X
n

×

C

2
⁢
n

wherein T 3n stands for the target value of the thickness of the nth metal layer,
X k stands for a coefficient of sheet resistance of the kth metal layer of the plurality of the metal layers versus capacitance of the kth capacitor unit of the plurality of the capacitor units,
X n stands for a coefficient of sheet resistance of the nth metal layer versus capacitance of the nth capacitor unit,
T 2k stands for a value of a monitored thickness of the kth metal layer,
C 2k stands for a value of a monitored critical dimension of the kth metal layer,
C 2n stands for a value of a monitored critical dimension of the nth metal layer,
RS n stands for a design value of sheet resistance of the metal layers from the first metal layer to the nth metal layer of the plurality of the metal layers,
k is a positive integer, and
n is a positive integer larger than 1.

5. The manufacturing method of the capacitor structure according to claim 4 , wherein the design value of the sheet resistance of the metal layers from the first metal layer to the nth metal layer of the plurality of the metal layers is calculated by a following equation:

R
⁢

S
n

=

∑

k
=
1

n

⁢

X
k

×

T

1
⁢
k

×

C

1
⁢
k

wherein T 1k stands for a design value of a thickness of the kth metal layer, and C 1k stands for a design value of a critical dimension of the kth metal layer.

6. The manufacturing method of the capacitor structure according to claim 4 , wherein each of the plurality of the capacitor units comprises a metal-oxide-metal (MOM) capacitor unit.

7. The manufacturing method of the capacitor structure according to claim 4 , wherein the plurality of the capacitor units are electrically connected with one another.

8. The manufacturing method of the capacitor structure according to claim 4 , wherein the plurality of the capacitor units are electrically connected with one another in parallel.

9. The manufacturing method of the capacitor structure according to claim 3 , wherein the target value of the thickness of the first electrically conductive layer is calculated by a following equation:

T

3
⁢
A

=

Assignees

• United Semiconductor Xiamen Co Ltd

Inventors

• Chang Wei-Chun
• Huang Han-Min
• Jhang You-Di
• Tan wen yi

Classifications

• H10D1/711

  having non-planar surfaces, e.g. formed by texturisation · CPC title

• H10D1/694 Primary

  comprising noble metals or noble metal oxides · CPC title

• H10D1/684 Primary

  the dielectrics comprising multiple layers, e.g. comprising buffer layers, seed layers or gradient layers · CPC title

• H10D1/68 Primary

  Capacitors having no potential barriers · CPC title

• H01L28/65

  Electricity · mapped topic