Structure of memory device and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-11024672-B2
Application number	US-201916418770-A
Country	US
Kind code	B2
Filing date	May 21, 2019
Priority date	Apr 15, 2019
Publication date	Jun 1, 2021
Grant date	Jun 1, 2021

Abstract

A structure of memory device is provided. The structure of memory device includes a transistor formed on a substrate. A contact structure is disposed on a source/drain region of the transistor. A conductive layer is disposed on the contact structure. Four memory structures is disposed on the conductive layer to form a quadrilateral structure.

First claim

What is claimed is:

1. A structure of memory device, comprising:
a transistor, formed on a substrate;
a contact structure, disposed on a source/drain region of the transistor;
a conductive layer, disposed on the contact structure;
four memory structures, wherein a first electrode of each of the four memory structures is disposed on the conductive layer to form a quadrilateral structure;
a first pair of interconnection lines, respectively connected to second electrodes of the first pair of the four memory structures; and
a second pair of interconnection lines, respectively connected to second electrodes of the second pair of the four memory structures,
wherein the first pair of interconnection lines and the second pair of interconnection lines are extending along two different directions.

2. The structure of memory device as recited in claim 1 , wherein two of the four memory structures extend along a first direction as a first pair, and another two of the four memory structures extend along a second direction as a second pair, the first direction intersects the second direction.

3. The structure of memory device as recited in claim 1 , further comprising four interconnection lines, respectively connected to the four memory structures.

4. The structure of memory device as recited in claim 1 , wherein the first pair of interconnection lines is higher than the second pair of interconnection lines.

5. The structure of memory device as recited in claim 4 , wherein the first pair of interconnection lines has a protruding portion to contact the first pair of the four memory structures.

6. The structure of memory device as recited in claim 1 , wherein the contact structure comprises at least one contact pole.

7. The structure of memory device as recited in claim 1 , wherein each of the four memory structures is a resistive memory structure or a phase-change memory structure.

8. The structure of memory device as recited in claim 1 , wherein the conductive layer is a single layer.

9. The structure of memory device as recited in claim 1 , wherein the conductive layer comprises:
a metal layer, disposed on the contact structure; and
a via layer, disposed on the metal layer, wherein the first pair of memory structures and the second pair of memory structures are disposed on the via layer.

10. The structure of memory device as recited in claim 9 , wherein the via layer has a concave at a central region surrounded by a peripheral region, and the four memory structures are disposed on the via layer at the peripheral region.

Assignees

• United Microelectronics Corp

Inventors

• Chen Chung-Tse
• Chen Ko-Chi
• Chang Tzu-Yun

Classifications

• H10N70/231

  based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect · CPC title

• H10N70/826

  adapted for essentially vertical current flow, e.g. sandwich or pillar type devices · CPC title

• H10N70/20

  Multistable switching devices, e.g. memristors · CPC title

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title

• G11C13/0002

  using resistive RAM [RRAM] elements · CPC title