Methods and systems for highly optimized memristor write process

Patent metadata

Field	Value
Publication number	US-11024379-B2
Application number	US-201916667773-A
Country	US
Kind code	B2
Filing date	Oct 29, 2019
Priority date	Oct 29, 2019
Publication date	Jun 1, 2021
Grant date	Jun 1, 2021

Abstract

Systems and methods for providing write process optimization for memristors are described. Write process optimization circuitry manipulates the memristor's write operation, allowing the number of cycles in the write process is reduced. Write process optimization circuitry can include write current integration circuitry that measures an integral of a write current over time. The write optimization circuitry can also include shaping circuitry. The shaping circuitry can shape a write pulse, by determining the pulse's termination, width, and slope. The write pulse is shaped depending upon whether the target memristor device exhibits characteristics of “maladroit” cells or “adroit” cells. The pulse shaping circuitry uses the integral and measured write current to terminate the write pulse in a manner that allows the memristor, wherein having maladroit cells and adroit cells, to reach a target state. Thus, utility of memristors is enhanced by realizing an optimized write process with decrease latency and improved efficiency.

First claim

What is claimed is:

1. A circuit for optimizing a write process for a memristor, comprising: current monitoring circuitry to monitor a write current corresponding to the memristor; current integration circuitry measuring the monitored write current corresponding to the memristor over a period of time; and voltage pulse shaping circuitry determining, based on the measured write current, a width and a termination point of a write pulse corresponding to the write current applied during the write process for the memristor such that a number of cycles during the write process is minimized.

2. The circuit of claim 1 , wherein the current integration circuitry measures an integral of the monitored write current corresponding to the memristor during the write process for the memristor over the period of time.

3. The circuit of claim 2 , wherein the integral of the monitored write current represents a target current corresponding to a first target state for a first population of cells for memristors and a second target state for a second population of cells for memristors during the write process of the memristor.

4. The circuit of claim 3 , wherein the voltage pulse shaping circuitry determines the width and a slope of the write pulse in a manner that causes a divergence between the first population of cells for memristors and the second population of cells for memristors.

5. The circuit of claim 4 , wherein the voltage pulse shaping circuitry shapes the write pulse in accordance with the determined width and an experimentally known slope, and the current monitoring circuitry monitors an adjusted write current corresponding to the shaped write pulse.

6. The circuit of claim 5 , wherein the first population of cells for memristors comprises adroit cells that reach the first target state within a single write cycle and the second population of cells for memristors comprises maladroit cells that are associated with additional write cycles to reach the second target state.

7. The circuit of claim 6 , wherein the adjusted write current is indicative of whether the memristor is characteristic of the first population of cells for memristors or the second population of cells for memristors.

8. The circuit of claim 7 , wherein the voltage pulse shaping circuitry terminates the shaped write pulse when the adjusted write current indicates that the memristor is characteristic of the first population of cells for memristors, the adjusted write current value meets the current compliance limit and the integral of the adjusted write current meets a determined threshold.

9. The circuit of claim 7 , wherein the voltage pulse shaping circuitry extends the shaped write pulse prior to termination when the adjusted write current indicates that the memristor is characteristic of the second population of cells of memristors, and terminates the shaped write pulse after the adjusted write current value meets the current compliance limit, and after the integral of the adjusted write current meets a determined threshold.

10. The circuit of claim 9 , wherein the current compliance limit is reached within the minimized number of cycles during the write process.

11. The circuit of claim 10 , wherein the minimized number of cycles during the write process is less than the additional write cycles associated with the second target state, minimizes the number of write cycles in the write process, and decreases a latency associated with the write process.

12. The circuit of claim 11 , wherein the minimized number of write cycles is a single cycle.

13. A method for optimizing a write process for a memristor, comprising: monitoring a write current corresponding to the memristor; measuring the monitored write current corresponding to memristor over a period of time; shaping a write pulse corresponding to the measured write current such that the measured current is indicative of a termination point of the write pulse where the memristor reaches a target state; and terminating the write pulse at the termination point such that a number of cycles during a write process for the memristor is minimized.

14. The method of claim 13 , comprises:
measuring an integral of the monitored write current over the period of time.

15. The method of claim 14 , comprising:
terminating the write pulse when the monitored write current is at least equal to the current compliance limit and the integral of the monitored write current is at least equal to a threshold value.

16. A circuit for optimizing a write process for a memristor, comprising: the memristor, wherein the memristor comprises a cell; a write pulse circuit coupled to the memristor, wherein the write pulse circuit applies a write pulse to the memristor during a write process; and a write processes optimization circuit coupled to the write pulse circuit, wherein the write processes optimization circuits comprises pulse width and termination circuitry to receive measured write current from write current monitoring circuitry, and shape the write pulse by terminating the write pulse when the measured write current is at least equal to a current compliance limit such that the cell of the memristor reaches a target state in a minimized number of write cycles indicated by signal output from current integration circuitry being at least equal to a threshold value.

17. The circuit of claim 16 , wherein the cell of the memristor corresponds to a first population of cells for memristors that reach a first target state in a single write cycle, or a second population of cells for memristors that reach a second target state in a number of write cycles that are larger than a single write cycle.

18. The circuit of claim 17 , wherein the write process optimization circuit comprises:
current integration circuitry outputting a signal representing an integral of the write pulse corresponding to the memristor over time.

19. The circuit of claim 18 , wherein the write process optimization circuit comprises:
current monitoring circuitry, wherein the current monitoring circuitry measures a write current corresponding to the write pulse.

Assignees

• Hewlett Packard Entpr Dev Lp

Inventors

• Sharma Amit
• Strachan John Paul
• Kumar Suhas
• Graves Catherine
• Foltin Martin
• Warner Craig

Classifications

• G06N3/063

  using electronic means · CPC title

• G11C2213/15

  Current-voltage curve · CPC title

• G11C2013/009

  Write using potential difference applied between cell electrodes · CPC title

• G11C2013/0092

  Write characterized by the shape, e.g. form, length, amplitude of the write pulse · CPC title

• G11C13/0028 Primary

  Word-line or row circuits · CPC title