Voltage-mode bit line precharge for random-access memory cells

Patent metadata

Field	Value
Publication number	US-11024373-B2
Application number	US-201916670633-A
Country	US
Kind code	B2
Filing date	Oct 31, 2019
Priority date	Sep 12, 2019
Publication date	Jun 1, 2021
Grant date	Jun 1, 2021

Abstract

Circuits and methods are disclosed for voltage-mode bit line precharge for random-access memory cells. A circuit includes an array of random access memory cells; a low-impedance voltage source configured to provide a precharge voltage; and a control circuit configured to precharge a bit line of one of the random access memory cells to the precharge voltage using the low-impedance voltage source prior to reading the one of the random access memory cells.

First claim

What is claimed is:

1. A memory circuit comprising:
an array of random access memory cells;
a low-impedance voltage source configured to provide a precharge voltage; and
a control circuit configured to precharge a bit line of one of the random access memory cells to the precharge voltage using the low-impedance voltage source prior to reading the one of the random access memory cells such that a current flowing through the one of the random access memory cells does not exceed V PRE /R, wherein V PRE is the precharge voltage and R is a resistance of the one of the random access memory cells.

2. The memory circuit of claim 1 , further comprising:
an on/off switch disposed between the low-impedance voltage source and the bit line of the one of the random access memory cells;
wherein the control circuit is configured to electrically couple the low-impedance voltage source to the bit line until the bit line reaches the precharge voltage, and to electrically decouple the low-impedance voltage source from the bit line prior to reading the one of the random access memory cells.

3. The memory circuit of claim 1 , wherein the low-impedance voltage source is a high-gain low-impedance voltage source.

4. The memory circuit of claim 3 , wherein the low-impedance voltage source comprises a unity-gain amplifier.

5. The memory circuit of claim 1 , wherein the random access memory cells are resistive random access memory cells.

6. The memory circuit of claim 5 , wherein a magnitude of the precharge voltage is selected such that a read time of the resistive random access memory cells when off is approximately equal to a read time of the resistive random access memory cells when on.

7. The memory circuit of claim 5 , wherein each of the resistive random access memory cells comprises:
a three-terminal access element; and
a resistive memory element coupled between the three-terminal access element and a respective bit line.

8. The memory circuit of claim 7 , wherein:
a first terminal of the three-terminal access element is coupled to one of a plurality of word lines;
a second terminal of the three-terminal access element is coupled to one of a plurality of source lines; and
the resistive memory element is coupled between a third terminal of the three-terminal access element and the one of the plurality of the bit lines.

9. The memory circuit of claim 1 , further comprising:
a sense amplifier configured to read the random access memory cells.

10. A method for reading a random access memory cell, the method comprising:
providing a precharge voltage from a low-impedance voltage source to a bit line of the random access memory cell such that a current flowing through the random access memory cell does not exceed V PRE /R, wherein V PRE is the precharge voltage and R is a resistance of the random access memory cell; and
reading the random access memory cell subsequent to a voltage of the bit line reaching the precharge voltage.

11. The method of claim 10 , further comprising:
ceasing to provide the precharge voltage from the low-impedance voltage source to the bit line of the random access memory cell prior to reading the random access memory cell.

12. The method of claim 10 , further comprising:
electrically coupling the low-impedance voltage source to the bit line until the bit line reaches the precharge voltage; and
electrically decoupling the low-impedance voltage source from the bit line prior to reading the random access memory cell.

13. The method of claim 10 , wherein the voltage source comprises a low-impedance voltage source.

14. The method of claim 13 , wherein the low-impedance voltage source comprises a unity-gain amplifier.

15. The method of claim 1 , wherein the random access memory cell is a resistive random access memory cell.

16. The method of claim 15 , wherein a magnitude of the precharge voltage is selected such that a read time of the resistive random access memory cell when off is approximately equal to a read time of the resistive random access memory cell when on.

17. The method of claim 16 , wherein the resistive random access memory cell comprises:
a three-terminal access element; and
a resistive memory element coupled between the three-terminal access element and the bit line.

18. The method of claim 17 , wherein:
a first terminal of the three-terminal access element is coupled to a word line;
a second terminal of the three-terminal access element is coupled to a source line; and
the resistive memory element is coupled between a third terminal of the three-terminal access element and the bit line.

Assignees

• Hefei Reliance Memory Ltd

Inventors

• Manea Danut

Classifications

• G11C5/14

  Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} · CPC title

• G11C11/34

  using semiconductor devices · CPC title

• G11C11/40

  using transistors · CPC title

• G11C11/409

  Read-write [R-W] circuits · CPC title

• G11C11/4063 Primary

  Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing · CPC title