Pseudo-asynchronous digital circuit design

Patent metadata

Field	Value
Publication number	US-11023632-B2
Application number	US-201716313901-A
Country	US
Kind code	B2
Filing date	Jun 29, 2017
Priority date	Jun 29, 2016
Publication date	Jun 1, 2021
Grant date	Jun 1, 2021

Abstract

A logic element includes a logic block, a supply voltage input, switchable power gates and a gate selector. The logic block implements a logic function on input data to obtain at least one output data signal. The switchable power gates transfer a supply voltage from the supply voltage input to the logic block in accordance with respective gate control signals. At least two of the power gates have different respective electrical properties. The gate selector switches on differing ones of the power gates in accordance with gate selection data.

First claim

What is claimed is:

1. A logic element comprising:
a logic block, adapted to implement a logic function on input data to obtain at least one output data signal;
a supply voltage input;
a plurality of switchable power gates connected to said supply voltage input and to said logic block, adapted to transfer a supply voltage from said supply voltage input to said logic block in accordance with respective gate control signals, at least two of said power gates having a different respective electrical properties; and
a gate selector associated with said power gates, adapted to switch on differing ones of said power gates in accordance with gate selection data, said gate selection data comprising at least one of random data and at least some of said input data.

2. A logic element according to claim 1 , wherein, for each set of gate selection data, said gate selector is adapted to switch on a single one of said power gates.

3. A logic element according to claim 1 , wherein said gate selection data comprises functions of said input data.

4. A logic element according to claim 1 , wherein said gate selector is further adapted to switch on said differing ones of said power gates per cycle of a clock signal.

5. A logic element according to claim 1 , wherein said gate selector is further adapted to switch on said differing ones of said power gates a plurality of times during a cycle of a clock signal.

6. A logic element according to claim 1 , wherein at least two of said power gates have different respective voltage thresholds.

7. A logic element according to claim 1 , wherein said logic element comprises a logic circuit and said supply voltage is input into said logic circuit from an external voltage source.

8. A logic element according to claim 1 , wherein said supply voltage input comprises a plurality of input connections connected in parallel to said supply voltage, wherein at least some of said power gates transfer said supply voltage to said logic block from respective input connections.

9. A logic element according to claim 1 , wherein at least one of said power gates transfers said supply voltage to a respective electronic circuit element within said logic block.

10. A logic element according to claim 9 , wherein said respective electronic circuit element comprises one of:
a logic gate;
a plurality of interconnected logic gates;
a flip-flop;
a sampling element; and
a latch.

11. A logic element according to claim 1 , wherein said logic block is connected to a plurality of supply voltages, and at least two of said power gates transfer different respective supply voltages to said logic block.

12. A logic element according to claim 1 , wherein said logic block comprises combinational logic circuitry.

13. A logic element according to claim 1 , wherein said logic block comprises sequential logic circuitry.

14. A method comprising:
implementing, by a logic block, a logic function on input data, said logic block being connected to a supply voltage via a plurality of switchable power gates, at least two of said power gates having a different respective electrical properties; and
switching on differing ones of said power gates in accordance with gate selection data, said gate selection data comprising at least one of random data and at least some of said input data.

15. A method according to claim 14 , wherein for each set of gate selection data a single one of said power gates is switched on.

16. A method according to claim 14 , wherein said gate selection data comprises at least one function of said input data.

17. A method according to claim 14 , wherein said switching is per cycle of a clock signal.

18. A method according to claim 14 , wherein said switching is performed a plurality of times during a cycle of a clock signal.

19. A method according to claim 14 , wherein at least two of said power gates have different respective voltage thresholds.

20. A method according to claim 14 , wherein said supply voltage input comprises a plurality of input connections connected in parallel to said supply voltage, wherein at least some of said power gates transfer said supply voltage to said logic block from respective input connections.

21. A method according to claim 14 , wherein at least one of said power gates transfers said supply voltage to a respective electronic circuit element within said logic block.

22. A method according to claim 21 , wherein said respective electronic circuit element comprises one of:
a logic gate;
a plurality of interconnected logic gates;
a flip-flop;
a sampling element; and
a latch.

23. A method according to claim 14 , wherein said logic block is connected to a plurality of supply voltages, and at least two of said power gates connect said logic block to different respective supply voltages.

Assignees

• Univ Bar Ilan
• Bar Iian Univ

Inventors

• Levi Itamar
• Keren Osnat
• Fish Alexander

Classifications

• G06F2221/034

  Test or assess a computer or a system · CPC title

• G06F21/755

  with measures against power attack · CPC title

• G06F2119/06

  Power analysis or power optimisation · CPC title

• H03K19/0013

  in field effect transistor circuits · CPC title

• G06F21/75

  by inhibiting the analysis of circuitry or operation · CPC title