External trust cache

US11023587B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11023587-B2
Application numberUS-201816147712-A
CountryUS
Kind codeB2
Filing dateSep 29, 2018
Priority dateJun 3, 2018
Publication dateJun 1, 2021
Grant dateJun 1, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

In an embodiment, a system supports an external trust cache. That is, the trust cache is separate from the kernel image on the non-volatile storage in the system. During boot, the boot code may read the trust cache from the storage and write it to the working memory of the system (e.g. the Random Access Memory (RAM) forming the memory system in the system). The boot code may also validate the kernel image and write it to the memory system. The boot code may program a region register in the processor to define a region in the working memory that encompasses the kernel image and the trust cache, to protect the region from modification/tampering.

First claim

Opening claim text (preview).

What is claimed is: 1. A computer system comprising: a processor; a memory coupled to the processor; a non-volatile memory coupled to the processor, wherein the non-volatile memory stores: a kernel image, wherein the kernel image includes a plurality of instructions forming one or more code segments that, when executed on the processor, implement an operating system kernel on the computer system; and a trust cache separate from the kernel image, wherein the trust cache includes a plurality of hashes corresponding to a plurality of trusted code segments that are executable on the processor and are trusted by the operating system kernel, wherein the operating system kernel is configured to compute a first hash of a first trusted code segment of the plurality of trusted code segments in a first mode and is configured to determine whether or not to execute the first trusted code segment as trusted code on the computer system in the first mode based on a comparison of the first hash and the plurality of hashes in the trust cache; and a read-only memory (ROM) storing a boot code, wherein the boot code, when executed by the processor, causes the processor to: load the kernel image into the memory; and load the trust cache into the memory. 2. The computer system as recited in claim 1 wherein the boot code, when executed on the processor, causes the processor to: define a region of memory that encompasses the trust cache and the kernel image; and program a processor register that restricts access to the region. 3. The computer system as recited in claim 1 wherein the non-volatile memory further stores one or more secondary trust caches separate from the kernel image, wherein the secondary trust caches include a second plurality of hashes corresponding to a second plurality of trusted code segments that are executable on the processor and are trusted by the operating system kernel. 4. The computer system as recited in claim 3 wherein the boot code, when executed on the processor, causes the processor to: determine whether or not the computer system is booting in a second mode different from the first mode; load at least one of the one or more secondary trust caches into the memory in response to determining that the computer system is booting in the second mode; and inhibit loading the at least one of the one or more secondary trust caches in response to determining that the computer system is booting in the first mode. 5. The computer system as recited in claim 4 wherein the second mode is a debug mode. 6. The computer system as recited in claim 4 wherein the second mode is a diagnostic mode. 7. The computer system as recited in claim 4 wherein the at least one of the one or more secondary trust caches are loaded into the memory adjacent to the trust cache. 8. The computer system as recited in claim 1 wherein the plurality of trusted code segments are executed at user privilege level. 9. A non-transitory computer accessible storage medium storing: a kernel image, wherein the kernel image includes a plurality of instructions forming one or more code segments that, when executed on a computer, implement an operating system kernel on the computer; and a trust cache separate from the kernel image, wherein the trust cache includes a plurality of hashes corresponding to a plurality of trusted code segments that are executable on the computer and are trusted by the operating system kernel, wherein the operating system kernel is configured to compute a first hash of a first trusted code segment of the plurality of trusted code segments in a first mode and is configured to determine whether or not to execute the first trusted code segment as trusted code on the computer in the first mode based on a comparison of the first hash and the plurality of hashes in the trust cache. 10. The non-transitory computer accessible storage medium as recited in claim 9 further storing the plurality of trusted code segments. 11. The non-transitory computer accessible storage medium as recited in claim 10 further storing a boot code that, when executed on the computer, causes the computer to: load the kernel image into a memory in the computer; and load the trust cache into the memory. 12. The non-transitory computer accessible storage medium as recited in claim 11 wherein the boot code, when executed on the computer, causes the computer to: define a region of memory that encompasses the trust cache and the kernel image; and program a processor register that restricts access to the region. 13. The non-transitory computer accessible storage medium as recited in claim 9 wherein the operating system kernel, when executed on the computer, causes the computer to: execute the first trusted code segment responsive to a match between the first hash and one of the plurality of hashes in the trust cache. 14. The non-transitory computer accessible storage medium as recited in claim 9 wherein the operating system kernel, when executed on the computer, causes the computer to: prevent execution of the first trusted code segment responsive to a mismatch between the first hash and one of the plurality of hashes in the trust cache. 15. The non-transitory computer accessible storage medium as recited in claim 9 wherein the operating system kernel, when executed on the computer, causes the computer to: execute the first trusted code segment in an untrusted fashion responsive to a mismatch between the first hash and one of the plurality of hashes in the trust cache. 16. The non-transitory computer accessible storage medium as recited in claim 9 wherein the operating system kernel, when executed on the computer, causes the computer to: use an alternate mechanism to validate the first trusted code segment responsive to a mismatch between the first hash and one of the plurality of hashes in the trust cache. 17. The non-transitory computer accessible storage medium as recited in claim 9 further storing one or more secondary trust caches, wherein the one or more secondary trust caches are separate from the kernel image, and wherein the one or more secondary trust caches include a second plurality of hashes corresponding to a second plurality of trusted code segments that are executable on the computer and are trusted by the operating system kernel, wherein the one or more secondary trust caches are selectively loaded into a memory during boot of the computer. 18. A non-transitory computer accessible storage medium storing a plurality of instructions which, when executed on a computer, causes the computer to: load a kernel image into a memory in the computer from a non-volatile memory during a boot of the computer, wherein the kernel image includes a plurality of instructions forming one or more code segments that, when executed on the computer, implement an operating system kernel on the computer; and load a trust cache into the memory from the non-volatile memory, wherein the trust cache is separate from the kernel image on the non-volatile memory, and wherein the trust cache includes a plurality of hashes corresponding to a plurality of trusted code segments that are executable on the computer and are trusted by the operating system kernel, wherein the operating system kernel is configured to compute a first hash of a first trusted code segment of the plurality of trusted code segments in a first mode and is configured to determine whether or not to execute the first trusted code segment as trusted code on the computer in the first mode based on a comparison of the first

Assignees

Inventors

Classifications

  • in a hierarchical protection system, e.g. privilege levels, memory rings · CPC title

  • Loading of operating system · CPC title

  • G06F21/575Primary

    Secure boot · CPC title

  • to assure secure storage of data (address-based protection against unauthorised use of memory G06F12/14; record carriers for use with machines and with at least a part designed to carry digital markings G06K19/00) · CPC title

  • Security improvement · CPC title

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What does patent US11023587B2 cover?
In an embodiment, a system supports an external trust cache. That is, the trust cache is separate from the kernel image on the non-volatile storage in the system. During boot, the boot code may read the trust cache from the storage and write it to the working memory of the system (e.g. the Random Access Memory (RAM) forming the memory system in the system). The boot code may also validate the k…
Who is the assignee on this patent?
Apple Inc
What technology area does this patent fall under?
Primary CPC classification G06F12/1491. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jun 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 6 related publications on this page (citations in our corpus or others sharing the same primary CPC).