Self-morphing server platforms

Patent metadata

Field	Value
Publication number	US-11023258-B2
Application number	US-201615396077-A
Country	US
Kind code	B2
Filing date	Dec 30, 2016
Priority date	Dec 30, 2016
Publication date	Jun 1, 2021
Grant date	Jun 1, 2021

Abstract

Dynamically configurable server platforms and associated apparatus and methods. A server platform including a plurality of CPUs installed in respective sockets may be dynamically configured as multiple single-socket servers and as a multi-socket server. The CPUs are connected to a platform manager component comprising an SoC including one or more processors and an embedded FPGA. Following a platform reset, an FPGA image is loaded, dynamically configuring functional blocks and interfaces on the platform manager. The platform manager also includes pre-defined functional blocks and interfaces. During platform initialization the dynamically-configured functional blocks and interfaces are used to initialize the server platform, while both the pre-defined and dynamically-configured functional blocks and interfaces are used to support run-time operations. The server platform may be used in conventional rack architectures or implemented in a disaggregated rack architecture under which the single-socket and/or multi-socket servers are dynamically composed to employ disaggregated resources, such as memory, storage, and accelerators.

First claim

What is claimed is:

1. A server platform comprising:
a plurality n Central Processing Units (CPUs), where n is a number of two or more, each installed in a respective socket;
at least one coherent socket-to-socket link interconnecting a pair of sockets; and
a platform manager component, communicatively coupled to the plurality of CPUs, the platform manager including,
a plurality of predefined functional blocks and interfaces; and
a plurality of dynamically configurable functional blocks and interfaces,

wherein the plurality of dynamically configurable functional blocks and interfaces enable the server platform to be dynamically configured as n single-socket servers or an n-socket server, and
wherein the server platform includes n instances of at least a portion of the plurality of predefined functional blocks and interfaces.

2. The server platform of claim 1 , wherein the platform manager component comprises a System on a Chip (SoC) including at least one processor.

3. The server platform of claim 2 , wherein the plurality of dynamically configurable functional blocks and interfaces comprise programmable logic elements in a field programmable gate array (FPGA) that is embedded in the SoC.

4. The server platform of claim 1 , wherein the plurality of CPUs include n CPUs installed in n sockets, the server platform includes n instances of at least a portion of the dynamically configurable functional blocks and interfaces, and wherein the server platform is dynamically configurable as n single-socket servers and as an n-socket server.

5. The server platform of claim 1 , wherein the plurality of dynamically configurable functional blocks and interfaces include one or more platform telemetry controllers and interfaces coupled to at least one telemetry device.

6. The server platform of claim 1 , wherein the plurality of dynamically configurable functional blocks and interfaces includes a programmable flash storage device interface coupled to at least one flash storage device.

7. The server platform of claim 1 , wherein the plurality of dynamically configurable functional blocks and interfaces include a platform power sequence control block.

8. The server platform of claim 1 , wherein the plurality of dynamically configurable functional blocks and interfaces includes a deployment-specific customization block.

9. The server platform of claim 1 , wherein the plurality of dynamically configurable functional blocks include security primitives for platform firmware recovery.

10. A method performed by a server platform having a platform management component including a Field Programmable Gate Array (PFGA) coupled to a plurality of Central Processing Units (CPUs), each CPU installed in a respective socket, comprising:
dynamically configuring the server platform in a first configuration comprising a plurality of single socket servers by loading a first bitstream comprising a first FPGA image in the FPGA, causing the FPGA to implement a first plurality of functional blocks and interfaces to support boot up and run-time operations of the server platform in the first configuration;
initializing each of the plurality of single socket servers using at least one of the first plurality of functional blocks and interfaces;
performing run-time operations using the plurality of single socket servers;
one of resetting or shutting down the server platform;
dynamically reconfiguring the server platform as a multi-socket server platform including the plurality of CPUs by loading a second bitstream comprising a second FPGA image in the FPGA, causing the FPGA to implement a second plurality of functional blocks and interfaces to support boot up and run-time operations of the server platform in the second configuration comprising the multi-socket server;
initializing the multi-socket server using at least one of the second plurality of functional blocks and interfaces; and
performing run-time operations using the multi-socket server.

11. The method of claim 10 , wherein the management components comprises a System on a Chip (SoC) including an embedded FPGA, at least one processor, and a plurality of pre-defined functional blocks and interfaces, at least a portion of which have duplicate instances; the method further comprising: implementing respective instances of the at least a portion of the functional blocks and interfaces that have duplicate instances for respective single-socket servers when the server platform is configured in the first configuration as a plurality of single-socket servers.

12. The method of claim 10 , wherein the plurality of sockets are interconnected via at least one coherent socket-to-socket link, the method further comprising: utilizing the at least one coherent socket-to-socket link to implement the server platform as a Non-Uniform Memory Architecture (NUMA) server under the second configuration; and disabling the at least one coherent socket-to-socket link when the server platform is configured to operate as a plurality of single-socket servers.

13. The method of claim 10 , wherein the server platform is implemented in a pooled compute drawer of a disaggregated rack architecture including a rack in which a plurality of pooled system drawers are installed including the pooled compute drawer and at least one of a pooled memory drawer, a pooled storage drawer, and a pooled accelerator drawer, the method further comprising:
for at least one of the plurality of single-socket servers,
dynamically composing a single socket server including a CPU in the pooled compute drawer communicatively coupled to at least one of a memory device, storage device, and accelerator in at least one of the pooled memory drawer, the pooled storage drawer, and the pooled accelerator drawer.

14. A server platform comprising:
a plurality n Central Processing Units (CPUs), where n is a number of two or more, each installed in a respective socket;
at least one coherent socket-to-socket link interconnecting a pair of sockets; and
a platform manager component, communicatively coupled to the plurality of CPUs, the platform manager including,
a plurality of predefined functional blocks and interfaces; and
a plurality of dynamically configurable functional blocks and interfaces,

wherein the plurality of dynamically configurable functional blocks and interfaces enable the server platform to be dynamically configured as n single-socket servers or an n-socket server, and
wherein the server platform includes n instances of at least a portion of the plurality of dynamically configurable functional blocks and interfaces.

15. The server platform of claim 14 , wherein the platform manager component comprises a System on a Chip (SoC) including at least one processor.

16. The server platform of claim 15 , wherein the plurality of dynamically configurable functional blocks and interfaces comprise programmable logic elements in a field programmable gate array (FPGA) that is embedded in the SoC.

17. The server platform of claim 14 , wherein the plurality of CPUs include n CPUs installed in n sockets, the server platform includes n instances of at least a portion of the plurality of predefined functional blocks and interfaces, and wherein the server platform is dynamically configurable as n single-socket servers and as an n-socket server.

18. The server platform of claim 14 , wherein the plurality of dynamically configurable functional blocks and interfaces include one or more platform telemetry controllers and interfaces coupled to at least one telemetry device.

19. The

Assignees

• Intel Corp

Inventors

• Upasani Neeraj S
• Guillory Jeanne
• Powiertowski Wojciech
• Ghetie Sergiu D
• Kumar Mohan J
• Nachimuthu Murugasamy K

Classifications

• G06F8/654

  using techniques specially adapted for alterable solid state memories, e.g. for EEPROM or flash memories · CPC title

• G06F15/7867

  with reconfigurable architecture · CPC title

• H04L41/5054

  Automatic deployment of services triggered by the service manager, e.g. service implementation by automatic configuration of network components · CPC title

• H04L41/5096

  wherein the managed service relates to distributed or central networked applications · CPC title

• G06F9/4401

  Bootstrapping (security arrangements therefor G06F21/57) · CPC title