Voltage regulator

Patent metadata

Field	Value
Publication number	US-11022992-B2
Application number	US-201916720259-A
Country	US
Kind code	B2
Filing date	Dec 19, 2019
Priority date	Jan 4, 2019
Publication date	Jun 1, 2021
Grant date	Jun 1, 2021

Abstract

A voltage regulator can include: an input port with two terminals, and being configured to receive an input voltage; an output port with two terminals, and being configured to generate an output voltage, where the input port and the output port have a common ground potential; a group of input switches coupled in series between the two terminals of the input port, where a common node of every two adjacent input switches that form an input half-bridge topology is taken as an input switch node; at least one output half-bridge topology coupled between two terminals of the output port, where a common node of a high-side output switch and a low-side output switch in each output half-bridge topology is taken as an output switch node; and N storage capacitors, where each of the storage capacitors is coupled between one input switch node and one output switch node.

First claim

What is claimed is:

1. A voltage regulator, comprising:
a) an input port with two terminals, and being configured to receive an input voltage;
b) an output port with two terminals, and being configured to generate an output voltage, wherein the input port and the output port have a common ground potential;
c) a group of input switches coupled in series between the two terminals of the input port, wherein a common node of every two adjacent input switches that form an input half-bridge topology is taken as an input switch node;
d) at least one output half-bridge topology coupled between two terminals of the output port, wherein a common node of a high-side output switch and a low-side output switch in each output half-bridge topology is taken as an output switch node;
e) N storage capacitors, wherein each of the storage capacitors is coupled between one input switch node and one output switch node, such that each path from the input port to the output port comprises at least one storage capacitor; and
f) wherein switching states of the input switches and the output switches are controlled to be switched to control charging and discharging states of the storage capacitors, such that a ratio of the input voltage to the output voltage is N, wherein N is a natural number not less than 1.

2. The voltage regulator of claim 1 , further comprising an output capacitor coupled between the two terminals of the output port to filter the output voltage.

3. The voltage regulator of claim 1 , wherein the switching states of the odd-numbered input switches and the switching states of the high-side output switches are identical, and the switching states of the even-numbered input switches and the switching states of the low-side output switches are identical.

4. The voltage regulator of claim 3 , wherein the switching states of the high-side output switches and the low-side output switches are complementary.

5. The voltage regulator of claim 3 , wherein a conduction phase difference between the high-side output switches and the low-side output switches is 180°.

6. The voltage regulator of claim 5 , wherein duty cycles of the high-side output switches and the low-side output switches are the same.

7. The voltage regulator of claim 1 , wherein when the number of the input switches is configured as 2N, N input half-bridge topologies are formed, and each common node of two input switches in each input half-bridge topology is taken as the input switch node.

8. The voltage regulator of claim 7 , wherein the voltage regulator further comprises N input capacitors, each of which is coupled to two terminals of a corresponding input half-bridge topology.

9. The voltage regulator of claim 7 , wherein first terminals of the N storage capacitors are respectively coupled to different input switch nodes.

10. The voltage regulator of claim 7 , wherein the number of the output half-bridge topology is 1, and second terminals of the N storage capacitors are coupled to the same output switch node.

11. The voltage regulator of claim 7 , wherein the high-side output switches are coupled to a positive terminal of the output port, and the low-side output switches are coupled to a negative terminal of the output port.

12. The voltage regulator of claim 7 , wherein the number of the output half-bridge topology is M, wherein M is not greater than N, and each of the output switch nodes is coupled to a second terminal of at least one storage capacitor.

13. The voltage regulator of claim 1 , wherein when the number of the input switches is configured as N+1, every two adjacent input switches form one input half-bridge topology, thereby forming N input switch nodes, wherein N is a natural number not less than 2.

14. The voltage regulator of claim 13 , wherein the number of the output half-bridge topology is not less than 2 and not greater than N, and the output half-bridge topologies comprise at least one first-type output half-bridge topology and at least one second-type output half-bridge topology, wherein the high-side output switch of the first-type output half-bridge topology is coupled to a positive terminal of the output port, and the low-side output switch of the second-type output half-bridge topology is coupled to a positive terminal of the output port.

15. The voltage regulator of claim 13 , wherein a first terminal of each of the storage capacitors is respectively coupled to a different input switch node.

16. The voltage regulator of claim 13 , wherein each of the output switch nodes is coupled to a second terminal of at least one storage capacitor.

17. The voltage regulator of claim 16 , wherein every two adjacent storage capacitors are coupled to different types of the output half-bridge topologies.

18. The voltage regulator of claim 17 , wherein when N is an odd number, the output half-bridge topologies coupled to the second terminals of the odd-numbered storage capacitors are of the same type with the output half-bridge topology coupled to the second terminal of the Nth storage capacitor, and the output half-bridge topologies coupled to the second terminals of the even-numbered storage capacitors are of different types with the output half-bridge topology coupled to the second terminal of the Nth storage capacitor.

19. The voltage regulator of claim 17 , wherein when N is an even number, the output half-bridge topologies coupled to the second terminals of the odd-numbered storage capacitors are of different types with the output half-bridge topology coupled to the second terminal of the Nth storage capacitor, and the output half-bridge topologies coupled to the second terminals of the even-numbered storage capacitors are of the same type with the output half-bridge topology coupled the second terminal of the Nth storage capacitor.

Assignees

• Silergy Semiconductor Technology Hangzhou Ltd

Inventors

• Zhang Wang
• Zhao Chen
• Mao Lang

Classifications

• G05F1/44

  semiconductor devices only · CPC title

• H02M3/07

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

• H02M1/32 Primary

  Means for protecting converters other than automatic disconnection · CPC title

• G05F1/575 Primary

  characterised by the feedback circuit · CPC title