Detection of pulse width tampering of signals

Patent metadata

Field	Value
Publication number	US-11022637-B2
Application number	US-201916244364-A
Country	US
Kind code	B2
Filing date	Jan 10, 2019
Priority date	Jan 10, 2019
Publication date	Jun 1, 2021
Grant date	Jun 1, 2021

Abstract

A sensor system includes a sensor having a charge storage device controllably connected to a voltage source under control of a signal under test; and a readout circuit coupled to the charge storage device to determine whether the pulse width of the signal under test has changed greater than a threshold amount according to a voltage at the charge storage device. In some cases, the determination of whether the pulse width of the signal under test has changed includes determining whether the voltage satisfies a condition with respect to a comparison voltage. In some cases, the determination of whether the pulse width of the signal under test has changed is based on a propagation delay through a delay chain, where the propagation delay is dependent on the voltage.

First claim

What is claimed is:

1. A sensor system comprising:
a sensor comprising a charge storage device controllably connected to a voltage source under control of a signal under test, wherein the charge storage device is controllably connected to the voltage source by at least one switch;
a conditioning circuit coupled to the at least one switch, wherein the conditioning circuit is coupled to receive a command signal and the signal under test and output a transient-removed signal under test to the at least one switch; and
a readout circuit coupled to the charge storage device to determine whether a pulse width of the signal under test has changed greater than a threshold amount according to a voltage at the charge storage device, wherein the voltage at the charge storage device is related to the pulse width of the signal under test.

2. The sensor system of claim 1 , wherein the readout circuit comprises a comparator.

3. The sensor system of claim 1 , wherein the signal under test is a clock signal, a reset signal, a control signal, a status signal, a command bus signal or a data bus signal.

4. The sensor system of claim 1 , wherein the sensor further comprises a discharge switch coupled in parallel to the charge storage device.

5. The sensor system of claim 4 , wherein the discharge switch is controlled by an inverted signal of the signal under test.

6. The sensor system of claim 1 , wherein the readout circuit determines whether the pulse width of the signal under test has changed greater than the threshold amount by determining whether the voltage satisfies a condition with respect to a comparison voltage.

7. The sensor system of claim 6 , wherein the comparison voltage is from the same sensor but from another time.

8. The sensor system of claim 6 , wherein the comparison voltage is a reference voltage.

9. The sensor system of claim 6 , wherein the comparison voltage is a voltage from another charge storage device of another sensor.

10. A sensor system comprising:
a sensor comprising a charge storage device controllably connected to a voltage source under control of a signal under test; and
a readout circuit coupled to the charge storage device to determine whether the pulse width of the signal under test has changed greater than a threshold amount according to a voltage at the charge storage device, wherein the voltage at the charge storage device is related to a pulse width of the signal under test, wherein the readout circuit comprises a delay chain, wherein the readout circuit determines whether the pulse width of the signal under test has changed greater than the threshold amount based on propagation delay through the delay chain, the propagation delay being dependent on the voltage.

11. A sensor system comprising:
an inverter coupled to receive a signal under test and output an inverted signal under test;
a sensor comprising:
a charge storage device;
a first switch controlled by the signal under test to couple and decouple the charge storage device to a power supply; and
a second switch controlled by the inverted signal under test to bypass the charge storage device such that the charge storage device is discharged when the second switch is on; and

a conditioning circuit coupled to the first switch and the inverter, wherein the conditioning circuit is coupled to receive a command signal and the signal under test and output a transient-removed signal under test to the first switch and the inverter.

12. The sensor system of claim 11 , further comprising:
a readout circuit coupled to the charge storage device, wherein the readout circuit is configured to determine whether a pulse width of the signal under test has changed greater than a threshold amount according to a voltage at the charge storage device, wherein the voltage at the charge storage device is related to the pulse width of the signal under test.

13. The sensor system of claim 12 , wherein the readout circuit determines whether the pulse width of the signal under test has changed greater than the threshold amount by determining whether the voltage satisfies a condition with respect to a comparison voltage.

14. The sensor system of claim 13 , wherein the comparison voltage is a reference voltage.

15. The sensor system of claim 13 , wherein the comparison voltage is a voltage from another charge storage device of another sensor.

16. The sensor system of claim 13 , wherein the comparison voltage is from the same sensor but from another time.

17. The sensor system of claim 12 , wherein the readout circuit comprises a delay chain, wherein the readout circuit determines whether the pulse width of the signal under test has changed greater than the threshold amount based on propagation delay through the delay chain, the propagation delay being dependent on the voltage.

18. The sensor system of claim 12 , wherein the readout circuit comprises a comparator.

19. The sensor system of claim 11 , wherein the signal under test is a clock signal, a reset signal, a control signal, a status signal, a command bus signal or a data bus signal.

Assignees

• Advanced Risc Mach Ltd

Inventors

• Yanamadala Subbayya Chowdary
• Rien Mikael Yves Marie

Classifications

• G01R31/318588

  Security aspects · CPC title

• G01R31/31719 Primary

  Security aspects, e.g. preventing unauthorised access during test · CPC title

• G01R29/02

  Measuring characteristics of individual pulses, e.g. deviation from pulse flatness, rise time or duration · CPC title

• G01R29/023 Primary

  Measuring pulse width · CPC title

• G01R31/2882

  Testing timing characteristics · CPC title