Transmission phase measurement and calibration method utilizing higher-order frequency bins

Patent metadata

Field	Value
Publication number	US-11018728-B2
Application number	US-201916423499-A
Country	US
Kind code	B2
Filing date	May 28, 2019
Priority date	May 28, 2019
Publication date	May 25, 2021
Grant date	May 25, 2021

Abstract

A circuit includes a transmission channel that outputs a continuous-wave signal based on a reference signal, a transmit monitoring signal path that couples out a portion of the transmit signal as a monitoring signal, a test phase shifter that receives the reference signal and generates a phase-shifted signal based on a sequence of phase offsets applied to the reference signal, a phase mixer that mixes the phase-shifted signal and the monitoring signal to generate a mixer output signal including a plurality of direct current (DC) values, an analog-to-digital converter that samples the mixer output signal in order to provide a sequence of DC values; and a monitor circuit that applies a discrete Fourier transform (DFT) to the sequence of DC values to generate a plurality of DFT bins with corresponding DFT bin values, and generate compensated phase information of the transmission channel using at least two DFT bin values.

First claim

What is claimed is:

1. A circuit, comprising:
a transmission channel configured to output a continuous-wave signal based on a reference signal;
a transmit monitoring signal path configured to couple out a portion of the transmit signal as a transmit monitoring signal;
a test phase shifter configured to receive the reference signal and generate a phase-shifted signal based on a phase offset from a sequence of phase offsets applied to the received reference signal;
a phase mixer configured to mix the phase-shifted signal and the transmit monitoring signal to generate a mixer output signal comprising a plurality of direct current (DC) values;
an analog-to-digital converter (ADC) configured to sample the mixer output signal in order to provide a sequence of DC sample values, wherein each of the sequence of DC sample values corresponds to one phase offset of the sequence of phase offsets; and
a monitor circuit configured to apply a discrete Fourier transform (DFT) to the sequence of DC sample values to generate a plurality of DFT bins with corresponding DFT bin values, and generate compensated phase information of the transmission channel using at least two DFT bin values.

2. The circuit of claim 1 , wherein the at least two DFT bin values include a first harmonic component of the sequence of DC sample values located at a first DFT bin that follows a DC DFT bin and a third harmonic component of the sequence of DC sample values located at a third DFT bin that follows the DC DFT bin.

3. The circuit of claim 2 , wherein the first DFT bin is located adjacent to and between the DC DFT bin and a second DFT bin, and the third DFT bin is located adjacent to and between the second DFT bin and a fourth DFT bin.

4. The circuit of claim 2 , wherein the first harmonic component includes a measurement component and a first error component of the sequence of DC sample values and the third harmonic component includes a second error component of the sequence of DC sample values, the second error component being related to the first error component based on a predefined relationship.

5. The circuit of claim 4 , wherein the monitor circuit is configured to measure the second error component to derive the first error component based on the predefined relationship, and subtract the first error component from the first harmonic component to generate the compensated phase information.

6. The circuit of claim 2 , wherein the third harmonic component is an error component caused by a 2-period error introduced by the test phase shifter.

7. The circuit of claim 1 , wherein:
the transmission channel includes a transmission phase shifter, and
the circuit further comprises a control circuit configured to receive the compensated phase information and adjust a phase-shift setting of the transmission phase shifter based on the compensated phase information.

8. The circuit of claim 2 , wherein:
each DFT bin value includes a phase value and a magnitude value, and
the monitor circuit is configured to use the phase value and the magnitude value from the first DFT bin and the third DFT bin to calculate the compensated phase information.

9. The circuit of claim 8 , wherein:
the monitor circuit is configured to derive a first value based on the magnitude value of the third DFT bin, the phase value of the third DFT bin, and the phase value of the first DFT bin, use the first value to calculate a complex value, and use an angle of the complex value to derive the compensated phase information.

10. The circuit of claim 9 , wherein:
the monitor circuit is configured to calculate the complex value based on the magnitude value from the first DFT bin, the magnitude value from the third DFT bin, and the first value.

11. The circuit of claim 1 , wherein the sequence of DC sample values have a sinusoidal pattern.

12. The circuit of claim 1 , wherein the test phase shifter is an I/Q modulator.

13. The circuit of claim 1 , wherein the phase shifter introduces a 2-period phase error into the phase-shifted signal.

14. The circuit of claim 1 , wherein each of the plurality of DC values correspond to a different phase offset of the sequence of phase offsets.

15. The circuit of claim 14 , wherein the sequence of phase offsets is a stepwise rotation of a phase offset over one full rotation of 2π.

16. A method of measuring a transmission phase, the method comprising:
outputting a continuous-wave signal from a transmission channel based on a reference signal;
coupling out a portion of the transmit signal as a transmit monitoring signal;
generating a phase-shifted signal based on a phase offset from a sequence of phase offsets applied to the reference signal;
mixing the phase-shifted signal and the transmit monitoring signal to generate a mixer output signal comprising a plurality of direct current (DC) values;
sampling the mixer output signal in order to provide a sequence of DC sample values, wherein each of the sequence of DC sample values corresponds to one phase offset of the sequence of phase offsets;
applying a discrete Fourier transform (DFT) to the sequence of DC sample values to generate a plurality of DFT bins with corresponding DFT bin values; and
generating compensated phase information of the transmission channel based on at least two DFT bin values.

17. The method of claim 16 , wherein the at least two DFT bin values include a first harmonic component of the sequence of DC sample values located at a first DFT bin that follows a DC DFT bin and a third harmonic component of the sequence of DC sample values located at a third DFT bin that follows the DC DFT bin.

18. The method of claim 17 , wherein the first DFT bin is located adjacent to and between the DC DFT bin and a second DFT bin, and the third DFT bin is located adjacent to and between the second DFT bin and a fourth DFT bin.

19. The method of claim 17 , wherein the first harmonic component includes a measurement component and a first error component of the sequence of DC sample values and the third harmonic component includes a second error component of the sequence of DC sample values, the second error component being related to the first error component based on a predefined relationship.

20. The method of claim 19 , wherein generating the compensated phase information of the transmission channel comprises:
measuring the second error component;
deriving the first error component based on the measured second error component and the predefined relationship; and
subtracting the first error component from the first harmonic component to generate the compensated phase information.

21. The method of claim 16 , further comprising:
adjusting a phase-shift setting of a transmission phase shifter of the transmission channel based on the compensated phase information.

22. A method of calibrating an IQ modulator, the method comprising:
generating a continuous-wave signal based on a continuous-wave reference signal;
generating a sequence of phase-shifted signals based on a sequence of phase offsets applied to the reference signal;
mixing the sequence of phase-shifted signals and the continuous-wave signal to generate a sequence of mixer output signals;
sampling the sequence of mixer output signals;
determining a sequence of DC sample values from the sequence of mixer output signals, wherein each DC sample value of the sequence of DC sample values corresponds to one phase offset of the sequence of phase offsets;
applying a discrete Fourier transfor

Assignees

• Infineon Technologies Ag

Inventors

• Lang Oliver
• Arriola Werner
• Fiore Vincenzo
• Melzer Alexander

Classifications

• G01S13/931

  of land vehicles · CPC title

• G01S13/343

  using sawtooth modulation · CPC title

• G01S7/35

  Details of non-pulse systems · CPC title

• H04B1/48

  in circuits for connecting transmitter and receiver to a common transmission path, e.g. by energy of transmitter {(H04B1/46 takes precedence)} · CPC title

• G01S13/825

  with exchange of information between interrogator and responder · CPC title