Coarse delay lock estimation for digital DLL circuits

Patent metadata

Field	Value
Publication number	US-11018676-B2
Application number	US-201916392184-A
Country	US
Kind code	B2
Filing date	Apr 23, 2019
Priority date	Apr 2, 2016
Publication date	May 25, 2021
Grant date	May 25, 2021

Abstract

Digital delay locked loop circuits, devices systems, and associated methods are provided and described. Such devices, systems, and methods utilize an open loop measurement for establishing a coarse delay lock.

First claim

What is claimed is:

1. An electronic device, comprising:
delay-locked loop (DLL) circuitry including:
a pair of shift registers to receive a reference clock signal from a reference clock source, each of the shift registers including a flip flop;
a compare circuit coupled between the pair of shift registers to compare a number of positive clock edges of the reference clock signal to a number of negative clock edges of the reference clock signal within an initial delay test window; and
a state machine coupled to the flip flop of each of the shift registers to increase a duration of the initial delay test window by a delay increment if the number of positive clock edges does not equal the number of negative clock edges;
wherein, until the number of positive and negative clock edges in the delay test window are equal:
the pair of shift registers are to repeat receipt of the reference clock signal;
the compare circuit is to repeat comparison of the number of positive to negative clock edges; and
the state machine is to repeat the increase of the duration of the delay test window; and

wherein the state machine is to further lock a strobe signal to the reference clock signal with a delay equal to a total duration increase of the delay test window.

2. The device of claim 1 , wherein the state machine includes a closed negative feedback loop to:
maintain a locking of the strobe signal to the reference clock signal.

3. The device of claim 1 , further comprising a double data rate (DDR) compatible interface coupled to the DLL circuitry.

4. The device of claim 3 , wherein the initial delay test window has a duration equal to the DDR interface analog delay path.

5. The device of claim 1 , wherein the delay increment is a duration of at least one reference clock cycle.

6. The device of claim 1 , wherein, to compare the number of positive to negative clock edges, the compare circuit is further configured to:
pass the reference clock signal through the pair of shift registers, where one shift register is triggered on positive clock edges and the other shift register is triggered on negative clock edges; and
compare the number of positive clock edges passing through one of the pair of shift registers to the number of negative clock edges passing through the other of the pair of shift registers during the delay test window.

7. The device of claim 6 , wherein the DLL circuitry is further configured to:
send a start transition to the pair of shift registers to start the delay test window; and
send the start transition through an analog delay path and to the pair of shift registers to stop the delay test window.

Assignees

• Intel Corp

Inventors

• Wei Fangxing
• Chandan Khushal
• Shi Dan
• Allen Michael

Classifications

• H03L7/0816

  the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input · CPC title

• G11C7/14

  Dummy cell management; Sense reference voltage generators · CPC title

• G11C11/56

  using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency · CPC title

• H03L7/0814 Primary

  the phase shifting device being digitally controlled · CPC title

• H03L7/10

  for assuring initial synchronisation or for broadening the capture range · CPC title