Multi-function level finder for serdes

Patent metadata

Field	Value
Publication number	US-11018656-B1
Application number	US-201916691523-A
Country	US
Kind code	B1
Filing date	Nov 21, 2019
Priority date	Nov 21, 2019
Publication date	May 25, 2021
Grant date	May 25, 2021

Abstract

An illustrative receiver includes: a decision element that derives symbol decisions from a slicer input signal; an equalizer that converts a receive signal into the slicer input signal; a summer that combines the symbol decisions with the slicer input signal to produce an error signal; and a level finder that operates on said signals to determine thresholds at which each signal has a given probability of exceeding the threshold. One illustrative level finder circuit includes: a gated comparator and an asymmetric accumulator. The gated comparator asserts a first or a second gated output signal to indicate when an input signal exceeds or falls below a threshold with a programmable condition being met. The asymmetric accumulator adapts the threshold using up steps for assertions of the first gated output signal and down steps for assertions of the second gated output signal, with the up-step size being different than the down-step size.

First claim

What is claimed is:

1. A level finder circuit that comprises:
a gated comparator asserting a first gated output signal only when an input signal exceeds a threshold with a programmable condition being met and asserting a second gated output signal only when the input signal falls below the threshold with the programmable condition being met; and
an asymmetric accumulator adapting the threshold using up steps for assertions of the first gated output signal and down steps for assertions of the second gated output signal, the up steps having an up-step size, the down steps having a down-step size, and the up-step size being different than the down-step size.

2. The level finder circuit of claim 1 , wherein the gated comparator compares the input signal to multiple thresholds and conditionally asserts for each threshold one of two corresponding gated output signals indicating whether the input signal exceeds or falls below that threshold with a corresponding programmable condition being met.

3. The level finder circuit of claim 1 , wherein the gated comparator is one of multiple gated comparators operating in parallel on a parallel set of input signals to assert a respective first gated output signal in a parallel set of first gated output signals only when the respective input signal exceeds the threshold with the programmable condition being met and to assert a respective second gated output signal in a parallel set of second gated output signals only when the respective input signal falls below the threshold with the programmable condition being met.

4. The level finder circuit of claim 3 , further comprising a first summer that sums the parallel set of first gated output signals to provide the asymmetric accumulator with a combined first gated output signal; and a second summer that sums the parallel set of second gated output signals to provide the asymmetric accumulator with a combined second gated output signal.

5. The level finder circuit of claim 1 , wherein the gated comparator comprises matching logic for verifying the programmable condition, the programmable condition including one or more conditions in the list consisting of:
a symbol decision having a given value at a selected offset from a current symbol interval,
a symbol decision not having the given value at the selected offset from the current symbol interval,
a current symbol having a first specified value,
a preceding symbol having a second specified value, and
assertion of one or more matching criterion bypass signals.

6. The level finder circuit of claim 5 , further comprising a shift register that provides at least the current symbol and the preceding symbol to the gated comparator.

7. The level finder circuit of claim 1 , further comprising an input multiplexer that provides, as said input signal, a selectable one of: a receive signal, a slicer input signal, and an error signal, said receive signal, said slicer input signal, and said error signal being provided by an equalizer of a communications receiver.

8. The level finder circuit of claim 7 , wherein the equalizer is a decision feedback equalizer having at least one precomputation unit.

9. A level finder method that comprises:
asserting a first gated output signal only when an input signal exceeds a threshold with a programmable condition being met;
asserting a second gated output signal only when the input signal falls below the threshold with the programmable condition being met; and
adapting the threshold using up steps for assertions of the first gated output signal and down steps for assertions of the second gated output signal, the up steps having an up-step size, the down steps having a down-step size, and the up-step size being different than the down-step size.

10. The level finder method of claim 9 , wherein said first and second gated output signals are one pair in a set of gated output signal pairs, and wherein the method includes comparing the input signal to multiple thresholds and conditionally asserting for each threshold one of a corresponding pair of gated output signals in said set to indicate whether the input signal exceeds or falls below that threshold with a corresponding programmable condition being met.

11. The level finder method of claim 9 , wherein the input signal is in a set of input signals being processed in parallel to assert a respective first gated output signal in a parallel set of first gated output signals only when the respective input signal exceeds the threshold with the programmable condition being met and to assert a respective second gated output signal in a parallel set of second gated output signals only when the respective input signal falls below the threshold with the programmable condition being met.

12. The level finder method of claim 11 , further comprising summing the parallel set of first gated output signals to provide a combined first gated output signal; and summing the parallel set of second gated output signals to provide a combined second gated output signal.

13. The level finder method of claim 9 , wherein said asserting the first or second gated output signal includes testing the programmable condition, the programmable condition including one or more conditions in the list consisting of:
a symbol decision having a given value at a selected offset from a current symbol interval,
a symbol decision not having the given value at the selected offset from the current symbol interval,
a current symbol having a first specified value,
a preceding symbol having a second specified value, and
assertion of one or more matching criterion bypass signals.

14. The level finder method of claim 13 , further comprising storing at least the current symbol and the preceding symbol in a shift register.

15. The level finder method of claim 9 , further comprising providing, as said input signal, a selectable one of: a receive signal, a slicer input signal, and an error signal, said receive signal, said slicer input signal, and said error signal being provided by an equalizer of a communications receiver.

Assignees

• Credo Tech Group Ltd

Inventors

• Sun Junqing (Phil)

Classifications

• H04L25/061

  providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of DC offset (removal of DC offset in coupling arrangements H04L25/029, H04L25/0296) · CPC title

• H04L25/03312

  Arrangements specific to the provision of output signals · CPC title

• H04L25/03267 Primary

  with decision feedback equalisers · CPC title

• H04B10/695

  Arrangements for optimizing the decision element in the receiver, e.g. by using automatic threshold control · CPC title

• H04L27/02

  Amplitude-modulated carrier systems, e.g. using on-off keying; Single sideband or vestigial sideband modulation (H04L27/32 takes precedence) · CPC title