Audio amplifier with embedded buck controller for class-G application

US11018644B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11018644-B2
Application numberUS-201916695010-A
CountryUS
Kind codeB2
Filing dateNov 25, 2019
Priority dateNov 27, 2018
Publication dateMay 25, 2021
Grant dateMay 25, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An audio amplifier includes: a buck controller configured to control an output voltage at a first supply terminal, the output voltage selected from a set including a plurality of output voltages, where the output voltage takes a settling time to settle; a first audio bridge including: a class-AB driver stage coupled to the first supply terminal, and a delay insertion circuit configured to receive a processed digital stream and provide the processed digital stream to the class-AB driver stage a delay time after receiving the processed digital stream, where the delay time is based on the settling time; and an audio amplitude detector configured to detect a first peak amplitude in the first digital audio stream, where the buck controller is configured to select a lowest output voltage from the set that is higher than the first peak amplitude plus a headroom voltage.

First claim

Opening claim text (preview).

What is claimed is: 1. An audio amplifier comprising: a first supply terminal; a second supply terminal; a buck controller having a supply input configured to receive a battery voltage, the buck controller configured to control an output voltage at the first supply terminal, the output voltage being selected from a set comprising a plurality of output voltages, wherein the output voltage at the first supply terminal takes a settling time to settle when the buck controller changes the output voltage from a first voltage of the set to a second voltage of the set, the second voltage being higher than the first voltage; a first audio bridge having an input configured to receive a first digital audio stream and an output configured to be coupled to a first speaker, the first audio bridge comprising: a class-AB driver stage coupled to the first supply terminal and configured to be coupled to the first speaker, a digital signal processing circuit coupled to the input of the first audio bridge, and a delay insertion circuit configured to receive a processed digital stream from the digital signal processing circuit and configured to provide the processed digital stream to the class-AB driver stage a delay time after receiving the processed digital stream, wherein the delay time is based on the settling time; and an audio amplitude detector having an input coupled to the input of the first audio bridge and configured to detect a first peak amplitude in the first digital audio stream, wherein the buck controller is configured to select a lowest output voltage from the set that is higher than the first peak amplitude plus a headroom voltage. 2. The audio amplifier of claim 1 , wherein the headroom voltage is 2 V or lower. 3. The audio amplifier of claim 1 , wherein the set comprises three output voltages. 4. The audio amplifier of claim 1 , wherein an output voltage of the set is the battery voltage. 5. The audio amplifier of claim 1 , wherein the second supply terminal is coupled to ground. 6. The audio amplifier of claim 1 , further comprising: a high-side transistor coupled between the supply input of the buck controller and an intermediate node; a diode coupled between the second supply terminal and the intermediate node; and an inductor coupled between the intermediate node and the input of the first audio bridge. 7. The audio amplifier of claim 6 , wherein the buck controller, the first audio bridge are integrated in an integrated circuit, and wherein the high-side transistor, the diode, and the inductor are external to the integrated circuit. 8. The audio amplifier of claim 6 , further comprising a low-side transistor that comprises the diode. 9. The audio amplifier of claim 6 , wherein the diode is a Schottky diode. 10. The audio amplifier of claim 1 , further comprising: a second audio bridge having an input configured to receive a second digital audio stream and an output configured to be coupled to a second speaker, the second audio bridge comprising: a second class-AB driver stage coupled to the first supply terminal and configured to be coupled to the second speaker, a second digital signal processing circuit coupled to the input of the second audio bridge, and a second delay insertion circuit configured to receive a second processed digital stream from the digital signal processing circuit and configured to provide the second processed digital stream to the class-AB driver stage a second delay time after receiving the processed digital stream, wherein the second delay time based on the settling time; and a second audio amplitude detector having an input coupled to the input of the second audio bridge and configured to detect a second peak amplitude in the second digital audio stream, wherein the buck controller is configured to select a lowest output voltage from the set that is higher than the first peak amplitude plus the headroom voltage and is higher than the second peak amplitude plus the headroom voltage. 11. The audio amplifier of claim 1 , wherein the delay time is higher than or equal to the settling time. 12. An integrated circuit comprising: a first supply terminal; a second supply terminal; a battery supply terminal; a buck controller having a supply input coupled to the battery supply terminal, the buck controller configured to control an output voltage at the first supply terminal, the output voltage being selected from a set comprising a plurality of output voltages, wherein the output voltage at the first supply terminal takes a settling time to settle when the buck controller changes the output voltage from a first voltage of the set to a second voltage of the set, the second voltage being higher than the first voltage; a first audio bridge having an input configured to receive a first digital audio stream and an output configured to be coupled to a first speaker, the first audio bridge comprising: a class-AB driver stage coupled to the first supply terminal and configured to be coupled to the first speaker, a digital signal processing circuit coupled to the input of the first audio bridge, and a delay insertion circuit configured to receive a processed digital stream from the digital signal processing circuit and configured to provide the processed digital stream to the class-AB driver stage a delay time after receiving the processed digital stream, wherein the delay time is based on the settling time; and an audio amplitude detector having an input coupled to the input of the first audio bridge and configured to detect a first peak amplitude in the first digital audio stream, wherein the buck controller is configured to select a lowest output voltage from the set that is higher than the first peak amplitude plus a headroom voltage. 13. The integrated circuit of claim 12 , further comprising: a second audio bridge having an input configured to receive a second digital audio stream and an output configured to be coupled to a second speaker, the second audio bridge comprising: a second class-AB driver stage coupled to the first supply terminal and configured to be coupled to the second speaker, a second digital signal processing circuit coupled to the input of the second audio bridge, and a second delay insertion circuit configured to receive a second processed digital stream from the digital signal processing circuit and configured to provide the second processed digital stream to the class-AB driver stage a second delay time after receiving the processed digital stream, wherein the second delay time is equal to the delay time; and a second audio amplitude detector having an input coupled to the input of the second audio bridge and configured to detect a second peak amplitude in the second digital audio stream, wherein the buck controller is configured to select a lowest output voltage from the set that is higher than the first peak amplitude plus the headroom voltage and is higher than the second peak amplitude plus the headroom voltage. 14. The integrated circuit of claim 12 , wherein the delay time is higher than or equal to the settling time. 15. The integrated circuit of claim 12 , wherein the set comprises three buck output voltages and wherein the headroom voltage is 2 V or lower. 16. An integrated circuit comprising: a first supply terminal; a second supply terminal; a third supply terminal; a controller having a supply input coupled to the third supply terminal, the controller configured to control an output voltage at the first supply terminal, the output voltage being selected from a set comprising a plurality of output vol

Assignees

Inventors

Classifications

  • H03G3/3005Primary

    in amplifiers suitable for low-frequencies, e.g. audio amplifiers (H03G3/32, H03G3/34 take precedence) · CPC title

  • Circuits for transducers (arrangements for producing a reverberation or echo sound G10K15/08; amplifiers H03F) · CPC title

  • H03F3/68Primary

    Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics {(power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602)} · CPC title

  • being an amplifying element · CPC title

  • H03F3/217Primary

    Class D power amplifiers; Switching amplifiers · CPC title

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What does patent US11018644B2 cover?
An audio amplifier includes: a buck controller configured to control an output voltage at a first supply terminal, the output voltage selected from a set including a plurality of output voltages, where the output voltage takes a settling time to settle; a first audio bridge including: a class-AB driver stage coupled to the first supply terminal, and a delay insertion circuit configured to recei…
Who is the assignee on this patent?
Stmicroelectronics Shenzhen R&D Co Ltd, Stmicroelectronics Shenzen R&D Co Ltd
What technology area does this patent fall under?
Primary CPC classification H03G3/3005. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue May 25 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).