Signal processing module, especially for a neural network and a neuronal circuit

Patent metadata

Field	Value
Publication number	US-11017290-B2
Application number	US-201415037659-A
Country	US
Kind code	B2
Filing date	Nov 27, 2014
Priority date	Dec 18, 2013
Publication date	May 25, 2021
Grant date	May 25, 2021

Abstract

A signal processing module comprises at least one operational unit incorporating computation units, input and output interfaces able to be linked to a bus and a memory storing data destined for the computation units, the memory being organized so that each data word is stored column-wise over several addresses according to an order dependent on the application, a column having a width of one bit, the words being transferred in series to the computation units.

First claim

The invention claimed is:

1. A signal processing module, comprising:
a memory and at least one operational unit incorporating an amount of computation units, wherein input and output interfaces are able to be linked to a bus and the memory storing data destined for said computation units; and
a routing unit connected between said memory and the at least one operational unit,
wherein said memory (i) comprises a plurality of columns and (ii) is organized in such a way that each of a plurality of data words is stored column-wise over several addresses, the columns each having a width of one bit, the words being transferred in series to said computation units,
wherein an amount of the columns is determined based on the amount of the computation units,
wherein the signal processing module implements a set of neurons, and
wherein said routing unit (i) has a number of inputs at least equal to a number of a width in bits of said memory and (ii) is configured to receive, via each of the inputs, data from only a single column of the memory and to route the data words between said memory and the computation units, one and the same word being able to be routed to a plurality of the computation units.

2. The signal processing module as claimed in claim 1 , wherein each data word is stored column-wise over several addresses according to an order dependent on the application using said data.

3. The signal processing module as claimed in claim 2 , wherein said several addresses comprise address jumps.

4. The signal processing module as claimed in claim 1 , wherein each of the computation units is an arithmetic logic unit (ALU).

5. The signal processing module as claimed in claim 1 , wherein the routing unit comprises at least two other series of inputs/outputs able to be linked to circuits outside said module.

6. The signal processing module as claimed in claim 5 , wherein said inputs/outputs are able to be linked as inputs and outputs of the routing unit of another module identical to said module.

7. The signal processing module as claimed in claim 1 , wherein the routing unit performs all or part of the following operations: shifting of the bits of the data words; logical operations; expansion of the words.

8. The signal processing module as claimed in claim 1 , comprising a memory virtualization unit linked on the one hand in write and read mode to said memory and on the other hand to an external memory via a circuit of DMA type.

9. The signal processing module as claimed in claim 8 , wherein the memory virtualization unit performs operations of reorganization of said memory.

10. The signal processing module as claimed in claim 9 , wherein the operations of reorganization of said memory are done by duplication or change of order of the data between the columns of said memory.

11. The signal processing module as claimed in claim 1 , wherein the input and output interfaces communicate with said bus by a TDMA protocol.

12. The signal processing module as claimed in claim 7 , comprising a memory virtualization unit linked on the one hand in write and read mode to said memory and on the other hand to an external memory via a circuit of DMA type, wherein said memory allows independent accesses in read and write mode for the input interfaces, the virtualization unit and the routing unit.

13. The signal processing module as claimed in claim 1 , wherein it operates according to several independent synchronous zones, the operational unit operating in a first clock area, the input interface and the output interface operating in a second clock area.

14. The signal processing module as claimed in claim 13 , comprising a memory virtualization unit linked on the one hand in write and read mode to said memory and on the other hand to an external memory via a circuit of DMA type, wherein the memory virtualization unit operates in a third independent clock area.

15. The signal processing module as claimed in claim 1 , wherein the computation units execute the operations as a function of the value of a guard bit assigned to each of said units.

16. The signal processing module as claimed in claim 1 , wherein the operational unit comprises at least 32 computation units, said memory having a width of 32 bits.

17. The signal processing module as claimed in claim 1 , wherein the signal processing module is able to perform neuronal computations or signal digital processings, said memory storing at least results of the computations, coefficients of filters or of convolution products and synaptic coefficients.

18. A circuit able to implement a neural network, comprising at least one series of signal processing modules as claimed in claim 17 .

19. The circuit as claimed in claim 18 , wherein the signal processing modules are grouped together as branches, a branch being formed of a group of modules and of a dissemination bus, said modules being connected to said bus, a routing block linked to the dissemination buses of said branches performing at least routing and dissemination of the input and output data of said circuit to and from said branches.

Assignees

• Commissariat Energie Atomique

Inventors

• Duranton Marc
• Philippe Jean-Marc

Classifications

• G06N3/0464

  Convolutional networks [CNN, ConvNet] · CPC title

• G06V10/955

  using specific electronic processors · CPC title

• G06F12/02

  Addressing or allocation; Relocation (program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00) · CPC title

• G06N3/063 Primary

  using electronic means · CPC title

• G11C11/54

  using elements simulating biological cells, e.g. neuron · CPC title